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AR# 58604

7 Series Integrated Block Wrapper for PCI Express v2.2 - External ports updated when upgrading the core from v2.0/v2.1 to v2.2

Description

Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

The following changes in the external ports are found, even though v2.2 is not a major version release, when upgrading the 7 Series Integrated Block Wrapper for PCI Express core from v2.0/v2.1 to v2.2 in 2013.3:

removed port 'conf_clk'
removed port 'icap_ceb_user'
removed port 'icap_wrb_user'
removed port 'icap_din_bs_user'
removed port 'icap_dout_user'
added port 'user_app_rdy'
added port 'startup_cfgclk'
added port 'startup_cfgmclk'
added port 'startup_eos'
added port 'startup_preq'
added port 'startup_clk'
added port 'startup_gsr'
added port 'startup_gts'
added port 'startup_keyclearb'
added port 'startup_pack'
added port 'startup_usrcclko'
added port 'startup_usrcclkts'
added port 'startup_usrdoneo'
added port 'startup_usrdonets'
added port 'icap_clk'
added port 'icap_csib'
added port 'icap_rdwrb'
added port 'icap_i'
added port 'icap_o'

Solution

This is a known issue.

Users are advised to make sure they update the wrapper/supporting files accordingly to accommodate the above changes.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
12/03/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 58604
Date Created 11/29/2013
Last Updated 01/07/2014
Status Active
Type Known Issues
IP
  • 7 Series Integrated Block for PCI Express (PCIe)