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AR# 58608

7 Series FPGAs Transceivers Wizard Example Design v3.0 - Use of clocking resources to check for tx|rxoutclk

Description

The startup FSMs for RX and TX check that tx|rxoutclk is present before releasing the reset of the MMCM. This is done through one FF for pmaresetdone which is clocked directly with tx|rxoutclk.

The reset for the MMCM is only necessary when a MMCM is really used or has to be used. This reset is not used when using only BUFG/BUFH to generate the USRCLKs.

The usage of tx|rxoutclk directly infers BUFHCE as tx|rxoutclk have no direct clocking route path to FF.

So, for example, a 10 lane core which uses just one BUFG to generate TX|RXUSRCLK and TX|RXUSRCLK2, as they are the same frequency, will infer 20 BUFHCE which clock just 20 FF.

In another example, a 10 lane core with separate clocking for RX and TX, and the need of MMCM, would normally use 6 BUFG/BUFH and 2 MMCM, but it still infers the 20 BUFHCE which clock just 20 FF.

This is unnecessary and can cause congestion in real designs.

Solution

If a design runs into congestion errors due to clock routing, or runs out of clocking resources due to the inferred BUFHCE, the following can be done:

Cores, which use only BUFG/BUFH for the USRCLK generation, could use the USRCLK at the TX|RXOUTCLK input of the startup FSM (--> no additional BUFHCE inferred).
The change could be similar to the change with MMCM below, but just in the *_init module the connections to the TX|RXOUTCLK inputs of all startup FSMs needs to be changed similar to the following:

 ' .TXOUTCLK                       (gt0_txusrclk_in), '

For a multi lane core, the easiest way for the change here would be within the *_startup_fsm modules by replacing TX|RXOUTCLK with TX|RXUSRCLK in the code.
Here is an example for the *_tx_startup_fsm.v:

   always @(posedge TXOUTCLK,posedge gttxreset_i)
  begin
      if(gttxreset_i == 1'b1)
        txpmaresetdone_i <= `DLY 1'b0;
      else
        txpmaresetdone_i <= `DLY TXPMARESETDONE;
  end
----------->
   always @(posedge TXUSRCLK,posedge gttxreset_i)
  begin
      if(gttxreset_i == 1'b1)
        txpmaresetdone_i <= `DLY 1'b0;
      else
        txpmaresetdone_i <= `DLY TXPMARESETDONE;
  end

For cores, using an MMCM, only the tx|rxoutclk which drives the MMCM would be necessary to check. It would not be necessary to check tx|rxoutclk of each lane separately. The used tx|rxoutclk usually uses a BUG/BUFH to drive the input of a MMCM. The output of this BUFG/BUFH could be used to drive the TX|RXOUTCLK inputs of the startup FSMs; with this, there would also be no further BUFHCE inferred.

In the following example design, several modules need to be changed:

*_clock_module:
        define clkin1 (output of the BUFG driving the MMCM) as output
*_gt_usrclk_source:
        define clkin1 as output and connect to *_clock_module
*_support:
        connect clkin1 from *_gt_usrclk_source to *_init
*_init:
        define clkin1 as input and connect to TX|RXOUTCLK inputs of all startup FSMs
        here one example for TX again:

        .TXOUTCLK                       (gt0_txoutclk_i),
------------->
        .TXOUTCLK                       (clkin1),
AR# 58608
Date Created 12/02/2013
Last Updated 01/16/2014
Status Active
Type General Article
Devices
  • Virtex-7
  • Artix-7
  • Kintex-7
IP
  • 7 Series FPGAs Transceivers Wizard