We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 58631

14.7 System Generator - EDK Processor block does not work in .SLX model format models


When an EDP processor block is configured for HDL netlisting and saved as .slx format, if "Generate" HDL Netlist is started in the System Generate block, the following error occurs:

The imported XPS project (c:/test/microblaze.mdl/XPS/system.xmp) cannot be found
Error occured during "HDL Netlist Configuration"


This is a known issue with the EDK Processor block in System Generator models that are saved as .slx format.

To work around this issue, you have to save the models which use the EDK Processor Block in this configuration in .mdl format (instead of the default .slx format) starting from R2012a.

The same model works if it is saved as .mdl file, instead of .slx file.

You can change the format settings under: MATLAB/File/Preferences/Simulink/Launch Simulink Preferences/Simulinkn EDK generated pcore.
Preferences/File format for new models and libraries: slx/mdl (slx is default) to mdl.

AR# 58631
Date 12/20/2013
Status Active
Type Known Issues
  • System Generator for DSP - 14
  • System Generator for DSP - 14.7