Version Found: v2.0 Rev2
Version Resolved: See (Xilinx Answer 54025)
All VCS and IES simulations will fail for MIG 7 Series QDRII+, RLDRAMII, and RLDRAM3 multi-controller designs.
This is only an issue with multi-controller designs and Vivado and QuestaSim simulations work as expected.
If a work-around is needed, please contact Xilinx Technical Support.
12/18/2013 - Initial release