Table 1-27, of the VC707 Evaluation Board User Guide v1.3 (UG885), outlines the J35 VITA 57.1 FMC HPC connections.
U1 FPGA Pin N39 is listed twice. Is this correct?
There is a typo in Table 1-27 of UG885 (v1.3); N39 should only be listed once.
The corrected section of the table is as follows:
FMC1_HPC_LA10_N is connected to U1 FPGA Pin M39.
FMC1_HPC_LA14_P is connected to U1 FPGA Pin N39.
Table 1-27 has been updated in UG885 (v1.4) to correctly reflect this pinout.
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