UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58662

Artix-7 FPGA AC701 Evaluation Kit - UG952 (v1.2), DDR3 Interface Banks Information

Description

In the AC701 Evaluation Board for the Artix-7 FPGA User Guide v1.2 (UG952), it states the following on page 12:

"The DDR3 interface is implemented across I/O banks 32, 33, 34. Each bank is a 1.5V high-performance (HP) bank."

Is this accurate?

Solution

The XC7A200T does not have HP banks, so this statement in UG952 (v1.2) is not accurate.

It should read:

"The DDR3 interface is implemented across I/O banks 33, 34, and 35. Each bank is a 1.5V high-range (HR) bank."

This is corrected in v1.3 of (UG952).

AR# 58662
Date Created 12/04/2013
Last Updated 03/11/2015
Status Active
Type General Article
Boards & Kits
  • Artix-7 FPGA AC701 Evaluation Kit