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AR# 58670

2013.4 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2013.4 in a single location which allows you to see all IP changes without having to installing the Vivado Design Suite.

Solution

100G Ethernet (1.0)
 * Version 1.0
 * Initial release
 * CAUI10 mode supported
 * Note: This core is released for simulation only. Hardware implementation is not supported with this release.

32-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 3)
 * Zynq devices marked as production 
 * Fixed syntax error in wave.sv file

3GPP LTE Channel Estimator (2.0)
 * Version 2.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

3GPP LTE MIMO Decoder (3.0)
 * Version 3.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

3GPP LTE MIMO Encoder (4.0)
 * Version 4.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

3GPP Mixed Mode Turbo Decoder (2.0)
 * Version 2.0 (Rev. 3)
 * C model changes so that the C model can be used along with C models from other cores. This changes exported types and function names. See smoke test and c model .h for examples and prototypes.
 * Support for Kintex UltraScale devices at Pre-Production Status

3GPP Turbo Encoder (5.0)
 * Version 5.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

3GPPLTE Turbo Encoder (4.0)
 * Version 4.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

64-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 3)
 * Zynq devices marked as production 
 * Fixed syntax error in wave.sv file

7 Series FPGAs Transceivers Wizard (3.1)
 * Version 3.1
 * Reset FSM updates- removed the posedge detection logic for plllock
 * GTZ updates- added new line rate support and updated xdc file for the constraints
 * Increased the number of optional transceiver control and status ports
 * Added support for Artix-7 35T and Artix-7 50T devices

7 Series Integrated Block for PCI Express (3.0)
 * Version 3.0
 * Added XC7Z200TSBG484 device support
 * Added support Artix-7 35t, 50t and 75t devices
 * Added port level enablement for icap and startup signal interfaces
 * Added 3 new ports - pipe_rxstatus, pipe_eyescandataerror and pipe_dmonitordout to the transceiver debug interface
 * Added logic to power down CPLL until it is required during the PCIe link bring-up

AHB-Lite to AXI Bridge (2.1)
 * Version 2.1 (Rev. 2)
 * Enhanced support for IP Integrator
 * Kintex UltraScale Pre-Production support
 * Updated Example design to use Clocking Wizard to generate clocks

AXI 10G-Ethernet (1.1)
 * Version 1.1
 * Add GTHE2 support.
 * Set core state to Pre-production.
 * Move RX time stamping position closer to transceiver.

AXI AHBLite Bridge (2.1)
 * Version 2.1 (Rev. 2)
 * Updated Example design to use Clocking Wizard to generate clocks
 * Kintex UltraScale Pre-Production support

AXI APB Bridge (2.0)
 * Version 2.0 (Rev. 3)
 * Error messages in IPI have been improved to avoid any confusion
 * Kintex UltraScale Pre-Production support

AXI BFM Cores (5.0)
 * Version 5.0 (Rev. 1)
 * Enhanced IPI supports to take care of Critical Warnings
 * Kintex UltraScale Pre-Production support

AXI BRAM Controller (3.0)
 * Version 3.0 (Rev. 3)
 * Added support for Hamming Code
 * Added support for UltraScale devices

AXI CAN (5.0)
 * Version 5.0 (Rev. 3)
 * Updated false path constraint set.
 * Kintex UltraScale Pre-Production support

AXI Central Direct Memory Access (4.1)
 * Version 4.1 (Rev. 1)
 * Example design updated to use blk_mem_gen_v8_1
 * Example design updated to use clk_wiz_v5_1
 * Kintex UltraScale Pre-Production support

AXI Chip2Chip Bridge (4.1)
 * Version 4.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Added beta support for optional Aurora 64B66B interface
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) hierarchy updates

AXI Clock Converter (2.1)
 * Version 2.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Broadened core-level XDC timing constraints to cover all asynchronous CDCs (if any), regardless of target family implementation.

AXI Crossbar (2.1)
 * Version 2.1 (Rev. 1)
 * Support for UltraScale devices

AXI Data FIFO (2.1)
 * Version 2.1 (Rev. 1)
 * Support for UltraScale devices

AXI Data Width Converter (2.1)
 * Version 2.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Broadened core-level XDC timing constraints to cover all asynchronous CDCs (if any), regardless of target family implementation.

AXI DataMover (5.1)
 * Version 5.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) hierarchy updates
 * Example design now uses clk_wiz_v5_1 to generate clocks

AXI Direct Memory Access (7.1)
 * Version 7.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) hierarchy updates
 * Example design updated to use blk_mem_gen_v8_1
 * Example design updated to use clk_wiz_v5_1
 * Repackaged to improve internal automation, no functional changes

AXI EMC (2.0)
 * Version 2.0 (Rev. 3)
 * Updated the example design to use Block Memory Generator version 8.1.
 * Updated the Address maps form register type to memory.
 * Added support for XGUI 2.0.
 * Lint mandatory warnings fixed.
 * Kintex UltraScale Pre-Production support.
 * Default value of '0' has been added for parity input pin.

AXI EPC (2.0)
 * Version 2.0 (Rev. 3)
 * Example design updated to use Clocking Wizard to generate clocks
 * Kintex UltraScale Pre-Production support

AXI Ethernet (6.0)
 * Version 6.0
 * No changes

AXI Ethernet Buffer (2.0)
 * Version 2.0 (Rev. 2)
 * Kintex UltraScale Pre-Production support.

AXI Ethernet Clocking (2.0)
 * Version 2.0 (Rev. 1)
 * No changes

AXI EthernetLite (2.0)
 * Version 2.0 (Rev. 3)
 * Board support enabled only when board has MII as well as MDIO interfaces.
 * Create clock constraints added to IP XDC
 * Kintex UltraScale Pre-Production support
 * OOC xdc updated to reflect clock period as per user selected frequency in GUI
 * Repackaged to improve internal automation, no functional changes

AXI GPIO (2.0)
 * Version 2.0 (Rev. 3)
 * Board interface connection for GPIO2 enabled by default
 * Updated Example design to use Clocking Wizard to generate clocks
 * Kintex UltraScale Pre-Production support

AXI HWICAP (3.0)
 * Version 3.0 (Rev. 3)
 * Improved support for multiple instances
 * Kintex UltraScale Pre-Production support
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) hierarchy updates

AXI IIC (2.0)
 * Version 2.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support
 * Repackaged to improve internal automation, no functional changes

AXI Interconnect (2.1)
 * Version 2.1 (Rev. 1)
 * Support for UltraScale devices.

AXI Interrupt Controller (4.1)
 * Version 4.1
 * Added Interrupt Level Register to support nested interrupts.
 * Added validation of hexadecimal parameter syntax and length.

AXI Master Burst (2.0)
 * Version 2.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

AXI Master IPIF (3.0)
 * Version 3.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

AXI Memory Mapped To PCI Express (2.3)
 * Version 2.3
 * Added default configuration values for AXI and PCIe BARs
 * Added support for External PIPE Interface
 * Added XC7Z200TSBG484 device support
 * Added support for Artix-7 35t, 50t and 75t devices
 * Added 3 new ports - pipe_rxstatus, pipe_eyescandataerror and pipe_dmonitordout to the transceiver debug interface
 * Added logic to power down CPLL until it is required during the PCIe link bring-up
 * Fixed timing issue for x1gen1 configuration for Artix-7 devices
 * Fixed data reordering issue when Narrow Burst transfer is enabled

AXI Memory Mapped to Stream Mapper (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI Performance Monitor (5.0)
 * Version 5.0 (Rev. 1)
 * Repackaged the IP by adding default values to all the optional input ports and no functional changes
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) updates
 * Kintex UltraScale Pre-Production support

AXI Protocol Checker (1.1)
 * Version 1.1 (Rev. 1)
 * Support for UltraScale devices

AXI Protocol Converter (2.1)
 * Version 2.1 (Rev. 1)
 * Support for UltraScale devices

AXI Quad SPI (3.1)
 * Version 3.1 (Rev. 1)
 * Updated example design to use Block Memory Generator version 8.1
 * Kintex UltraScale Pre-Production Support
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) hierarchy updates

AXI Register Slice (2.1)
 * Version 2.1 (Rev. 1)
 * Support for UltraScale devices

AXI TFT Controller (2.0)
 * Version 2.0 (Rev. 3)
 * Added UltraScale device support
 * Added a parameter to enable/disable I2C interface in DVI mode
 * Kintex UltraScale Pre-Production support

AXI Timebase Watchdog Timer (2.0)
 * Version 2.0 (Rev. 3)
 * Updated Example design to use Clocking Wizard to generate clocks
 * Kintex UltraScale Pre-Production support

AXI Timer (2.0)
 * Version 2.0 (Rev. 3)
 * Updated Example design to use Clocking Wizard to generate clocks
 * Kintex7 UltraScale Pre-Production support

AXI Traffic Generator (2.0)
 * Version 2.0 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * BUFG addition in example design for timing improvement.
 * Enhanced to loop through traffic in advanced/basic modes.
 * Improved GUI speed and responsiveness.

AXI UART16550 (2.0)
 * Version 2.0 (Rev. 3)
 * Kintex UltraScale Pre-production support
 * Repackaged to improve internal automation, no functional changes

AXI USB2 Device (5.0)
 * Version 5.0 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI Uartlite (2.0)
 * Version 2.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

AXI Video Direct Memory Access (6.1)
 * Version 6.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Helper core ( generator) instantiation update to fix VCS simulator issue, no functional changes
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) hierarchy updates
 * Downgraded frequency related critical warning to warning in IP Integrator
 * Improved GUI speed and responsiveness, no functional changes
 * Example design and example design constraints update to address inter-clock violations
 * Example design now uses clk_wiz_v5_1 to generate clocks
 * Example design update to use blk_mem_gen_v8_1

AXI Virtual FIFO Controller (2.0)
 * Version 2.0 (Rev. 3)
 * Added support for UltraScale devices

AXI-Stream FIFO (4.0)
 * Version 4.0 (Rev. 3)
 * Added support for UltraScale devices

AXI4-Stream Accelerator Adapter (2.0)
 * Version 2.0 (Rev. 1)
 * Added support for UltraScale devices

AXI4-Stream Broadcaster (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Clock Converter (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Combiner (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Data FIFO (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Data Width Converter (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Interconnect (2.1)
 * Version 2.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Protocol Checker (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Register Slice (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Subset Converter (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

AXI4-Stream Switch (1.1)
 * Version 1.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Arbitrate on low TVALID cycles is now disabled if Arbitrate on max transfers is 1.  Parameter has no meaning in this configuration.
 * Arbitrate on low TVALID cycles must be greater than one if there are multiple slaves and multiple masters and Arbitrate on max transfers is not 1. This is to prevent deadlock situations.

AXI4-Stream to Video Out (3.0)
 * Version 3.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support
 * Automotive Zynq devices support

Accumulator (12.0)
 * Version 12.0 (Rev. 3)
 * GUI tooltips added for INIT values
 * Support for Kintex UltraScale devices at Pre-Production Status

Adder Subtracter (12.0)
 * Version 12.0 (Rev. 3)
 * Latency is now restricted to the output width. Previously the GUI allowed illegal values
 * Tooltips added to GUI
 * Support for Kintex UltraScale devices at Pre-Production Status

Asynchronous Sample Rate Converter (2.0)
 * Version 2.0 (Rev. 2)
 * No changes

Aurora 64B66B (9.1)
 * Version 9.1
 * Increased the number of optional transceiver control and status ports

Aurora 8B10B (10.1)
 * Version 10.1
 * Increased the number of optional transceiver control and status ports

Binary Counter (12.0)
 * Version 12.0 (Rev. 3)
 * Tooltips added to GUI
 * Support for Kintex UltraScale devices at Pre-Production Status

Block Memory Generator (8.1)
 * Version 8.1
 * The Primitive output registers are made "ON" by default in the stand alone mode
 * Added cascaded support for ltraScale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
 * Added support for UltraScale devices

CIC Compiler (4.0)
 * Version 4.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

CORDIC (6.0)
 * Version 6.0 (Rev. 3)
 * C model modified to be interoperable with C models from other cores. The xip_array_* structures and interface functions xip_array_<type>_get_data and xip_array_<type>_set_data are renamed xip_<core>_array_<type>_[]set|get]_data.
 * Support for Kintex UltraScale devices at Pre-Production Status

CPRI (8.1)
 * Version 8.1
 * Added version register.
 * Kintex UltraScale Pre-Production support.
 * Added optional transceiver control and status ports.
 * For IP Integrator, previous bus I/F names have been renamed for consistency. Upgraded IP Integrator designs using this core will require reconnection of the Bus I/F's.

Chroma Resampler (4.0)
 * Version 4.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

Clocking Wizard (5.1)
 * Version 5.1 (Rev. 1)
 * Added support for UltraScale devices
 * Updated Board Flow GUI to select the clock interfaces
 * Fixed issue with Stub file parameter error for BUFR output driver

Color Correction Matrix (6.0)
 * Version 6.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

Color Filter Array Interpolation (7.0)
 * Version 7.0 (Rev. 3)
 * Added support for UltraScale Architecture

Complex Multiplier (6.0)
 * Version 6.0 (Rev. 3)
 * Missing tooltips added to GUI.
 * Support for Kintex UltraScale devices at Pre-Production Status

Convolution Encoder (9.0)
 * Version 9.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

DDS Compiler (6.0)
 * Version 6.0 (Rev. 3)
 * Fixed issue in GUI regarding illegal Phase_Angle_Values when Rasterized Mode_of_Operation was selected.
 * Missing GUI tooltips added.
 * GUI dependency between DSP48_Use and Latency corrected.
 * Support for Kintex UltraScale devices at Pre-Production Status

DSP48 Macro (3.0)
 * Version 3.0 (Rev. 3)
 * Tooltips added for all GUI fields
 * Support for Kintex UltraScale devices at Pre-Production Status

DUC/DDC Compiler (3.0)
 * Version 3.0 (Rev. 3)
 * Added length validation for the Component Name parameter and increased its maximum length
 * Added a memory map definition for the SREG APB bus
 * Support for Kintex UltraScale devices at Pre-Production Status

Defective Pixel Correction (7.0)
 * Version 7.0 (Rev. 3)
 * Added support for UltraScale Architecture

Discrete Fourier Transform (4.0)
 * Version 4.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

DisplayPort (4.2)
 * Version 4.2
 * Added optional transceiver control and status ports
 * Added Software access to GT DRP
 * XDC File updates for Audio

Distributed Memory Generator (8.0)
 * Version 8.0 (Rev. 3)
 * Added support for UltraScale devices

Divider Generator (5.1)
 * Version 5.1 (Rev. 1)
 * Clock constraint removed from supplied out of context xdc file for cases with no registers
 * ACLKEN and ARESETN disabled and set to false on GUI when Latency is set to 0
 * Support for Kintex UltraScale devices at Pre-Production Status

ECC (2.0)
 * Version 2.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

Ethernet 1000BASE-X PCS/PMA or SGMII (14.1)
 * Version 14.1
 * Kintex UltraScale Pre-Production Support.
 * Increased the number of optional transceiver control and status ports.
 * GT updates for Series-7 transceivers (Tx/Rx startup FSM updates).

Ethernet PHY MII to Reduced MII (2.0)
 * Version 2.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support
 * Enhanced support for IP Integrator

FIFO Generator (11.0)
 * Version 11.0 (Rev. 1)
 * Added support for UltraScale devices
 * Common Clock Built-in FIFO is set as default implementation type only for UltraScale devices
 * Embedded Register option is always ON for Block RAM and Built-in FIFOs only for UltraScale devices
 * Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices

FIR Compiler (7.1)
 * Version 7.1 (Rev. 2)
 * Added work-around to the GUI for AR57785
 * Support for Kintex UltraScale devices at Pre-Production Status

Fast Fourier Transform (9.0)
 * Version 9.0 (Rev. 3)
 * Change to end of simulation message in demonstration testbench.
 * Support for Kintex UltraScale devices at Pre-Production Status

Fixed Interval Timer (2.0)
 * Version 2.0 (Rev. 2)
 * No changes

Floating-point (7.0)
 * Version 7.0 (Rev. 3)
 * Missing tooltips added to GUI
 * GUI fix for possible illegal Latency values
 * Support for Kintex UltraScale devices at Pre-Production Status

G.709 FEC Encoder/Decoder (2.1)
 * Version 2.1
 * Move to DSP48E2 wide xor for encoder and decoder
 * Support for Kintex UltraScale devices at Pre-Production Status
 * Added additional exit message to testbench

G.975.1 EFEC I.4 Encoder/Decoder (1.0)
 * Version 1.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

G.975.1 EFEC I.7 Encoder/Decoder (2.0)
 * Version 2.0 (Rev. 3)
 * Non-functional changes to hdl to reduce warnings in synthesis and simulation.
 * Support for Kintex UltraScale devices at Pre-Production Status

Gamma Correction (7.0)
 * Version 7.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support

Gmii to Rgmii (3.0)
 * Version 3.0
 * No changes

IBERT 7 Series GTH (3.0)
 * Version 3.0 (Rev. 3)
 * No Changes

IBERT 7 Series GTP (3.0)
 * Version 3.0 (Rev. 3)
 * No Changes

IBERT 7 Series GTX (3.0)
 * Version 3.0 (Rev. 3)
 * No Changes

IBERT 7 Series GTZ (3.1)
 * Version 3.1 (Rev. 1)
 * No Changes

ILA (Integrated Logic Analyzer) (3.0)
 * Version 3.0 (Rev. 1)
 * Kintex UltraScale Pre-Production support

IOModule (2.2)
 * Version 2.2
 * Added synchronization flip-flops on asynchronous interrupt inputs, which adds a two clock cycle latency by default

Image Characterization (3.00.a)
 * Version 3.00.a
 * No changes

Image Enhancement (8.0)
 * Version 8.0 (Rev. 2)
 * Kintex UltraScale Pre-Production support

Image Noise Reduction (6.0)
 * Version 6.0 (Rev. 3)
 * The Image Noise Reduction core has been superseded by the Image Enhancement core.  The Image Enhancement core (v8.0 or later) contains noise reduction functionality.

Image Statistics (6.0)
 * Version 6.0 (Rev. 3)
 * Added support for UltraScale Architecture

Interlaken (1.0)
 * Version 1.0
 * Initial release
 * 12 x 12.5Gbps supported
 * Note: This core is released for simulation only. Hardware implementation is not supported with this release.

Interleaver/De-interleaver (8.0)
 * Version 8.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

JESD204 (5.1)
 * Version 5.1
 * Kintex UltraScale Pre-Production support.
 * Fix register address decode offset for captured ILA and other lane-specific data. (AR 58089)
 * Added additional transceiver control and status ports
 * For IP Integrator, previous bus I/F names have been renamed for consistency. Upgraded IP Integrator designs using this core will require reconnection of the Bus I/F's.

JTAG to AXI Master (1.0)
 * Version 1.0 (Rev. 1)
 * Synthesis warning reduction

LMB BRAM Controller (4.0)
 * Version 4.0 (Rev. 2)
 * No changes

LTE DL Channel Encoder (3.0)
 * Version 3.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

LTE Fast Fourier Transform (2.0)
 * Version 2.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

LTE PUCCH Receiver (2.0)
 * Version 2.0 (Rev. 3)
 * Non-functional changes to GUI files.
 * Support for Kintex UltraScale devices at Pre-Production Status

LTE RACH Detector (2.0)
 * Version 2.0 (Rev. 3)
 * Tooltips added to GUI.
 * Support for Kintex UltraScale devices at Pre-Production Status

LTE UL Channel Decoder (4.0)
 * Version 4.0 (Rev. 3)
 * C model changes so that the C model can be used along with C models from other cores. This changes exported types and function names. See smoke test and c model .h for examples and prototypes.
 * Fixed for segmentation faults from the C model on Windows platforms.
 * Support for Kintex UltraScale devices at Pre-Production Status

Linear Algebra Toolkit (2.0)
 * Version 2.0 (Rev. 2)
 * No changes

Local Memory Bus (LMB) 1.0 (3.0)
 * Version 3.0 (Rev. 2)
 * No changes

Mailbox (2.0)
 * Version 2.0 (Rev. 2)
 * No changes

Memory Interface Generator (MIG 7 Series) (2.0)
 * Version 2.0 (Rev. 2)
 * Added OOC support
 * Added support for IES and VCS Simulators

Memory Interface Generator (MIG) (4.2)
 * Version 4.2
 * DDR4 design initial support for Kintex UltraScale Pre-Production devices.
 * DDR3 design initial support for Kintex UltraScale Pre-Production devices.

MicroBlaze (9.2)
 * Version 9.2 (Rev. 1)
 * Improved automatic assignment of cache addresses

MicroBlaze Debug Module (MDM) (3.0)
 * Version 3.0 (Rev. 3)
 * Added XDC constraints for DRCK and UPDATE internal clocks

MicroBlaze MCS (2.1)
 * Version 2.1
 * Updated with latest subcore versions

Motion Adaptive Noise Reduction (6.1)
 * Version 6.1
 * Kintex UltraScale Pre-Production support
 * Improved current and previous AXI4-Stream video stream synchronization. The core now waits for a start of frame (SOF) signal on the 'previous' input stream, coming from the VDMA, while dropping samples on the current input. After the SOF is captured, the previous channel is held up, while the core waits for SOF on the current input.
 * Similar synchronization mechanism is employed for EOF signals. The core now can recover from cable disconnect - reconnect, or the system starting with a partial frame.
 * Improved MTF function tables. MTF depth increased to 128 entries per table per luminance / chrominance channel (256 entries total per MTF table).
 * Improved MTF Initial coefficients cover a larger set of Gaussian noise variances.
 * MTF table update improved. A single write to address 0x100 updates an MTF entry, with MTF table ID, address, and data encoded into a single 32 bit word. This method enables partial updates.

Multiplier (12.0)
 * Version 12.0 (Rev. 3)
 * Fixed bug in generation of DSP48-based multipliers for UltraScale devices
 * Support for Kintex UltraScale devices at Pre-Production Status

Multiply Accumulator (3.0)
 * Version 3.0 (Rev. 2)
 * No changes

Multiply Adder (3.0)
 * Version 3.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

Mutex (2.0)
 * Version 2.0 (Rev. 2)
 * No changes

Object Segmentation (3.00.a)
 * Version 3.00.a
 * No changes

Peak Cancellation Crest Factor Reduction (5.0)
 * Version 5.0
 * Addition of Dynamic Cancellation Pulse(CP) computation Mode where CP is computed dynamically based on power and frequency for individual carriers. This is called Dynamic Mode. This mode is required only if incoming data is frequency hopping and/or power hopping.
 * In Dynamic Mode, Tuser field has been added to the AXI4 stream (s_axis_din_tuser) that contains control information for the Dynamic CP computation.
 * Static Mode is similar to  PC-CFR v4.0 where static Cancellation  Pulse coefficients can be loaded through AXI-Lite interface
 * Support for multiple air interfaces including frequency hopping MC-GSM up to 8 GSM carriers
 * Support for hard clipper final stage (optional)
 * GUI changes  include a new input field  Max Peak Detect Window instead of two earlier input fields Cancellation Pulse Length and Latency.  This change applies to both Static and Dynamic Mode
 * GUI Implementation tab also shows an AXI4 Stream port structure
 * C Model has also been updated to reflect the Dynamic CP computation.
 * For more information on the above changes, please refer to the product guide

Processor System Reset (5.0)
 * Version 5.0 (Rev. 3)
 * Added exdes.xdc file
 * Changed the associated resets for slowest_sync_clk
 * Kintex UltraScale Pre-Production support

QSGMII (3.1)
 * Version 3.1
 * Kintex UltraScale Pre-Production support
 * GT updates for Series-7 transceivers (RX/TX Startup FSM updates)
 * Increased the number of optional transceiver control and status ports

RAM-based Shift Register (12.0)
 * Version 12.0 (Rev. 3)
 * Missing tooltips added to GUI
 * GUI error on change of radix fixed.
 * Support for Kintex UltraScale devices at Pre-Production Status

RGB to YCrCb Color-Space Converter (7.1)
 * Version 7.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

RXAUI (4.1)
 * Version 4.1
 * Added support for UltraScale
 * Increased the number of optional transceiver control and status ports.

Reed-Solomon Decoder (9.0)
 * Version 9.0 (Rev. 3)
 * Change to end of simulation message in demonstration testbench.
 * Support for Kintex UltraScale devices at Pre-Production Status

Reed-Solomon Encoder (9.0)
 * Version 9.0 (Rev. 3)
 * Support for Kintex UltraScale devices at Pre-Production Status

S/PDIF (2.0)
 * Version 2.0 (Rev. 3)
 * Updated rtl files to refer sub cores from central area instead of local files
 * Kintex UltraScale Pre-Production support added

SDI RX to Video Bridge (1.0)
 * Version 1.0 (Rev. 1)
 * Changed DUT instance name in testbench

SMPTE 2022-1/2 Video over IP Receiver (1.0)
 * Version 1.0 (Rev. 1)
 * Added Demo test bench
 * Fixed bug on receiving packets with TS per IP = 1 at higher transport stream rate

SMPTE 2022-1/2 Video over IP Transmitter (1.0)
 * Version 1.0 (Rev. 1)
 * Added Demo test bench
 * Updated to handle random tready signal input to core, to comply with AXIS spec
 * Updated all the datapath  to 64bit to support low frequency sys_clk

SMPTE SD/HD/3G-SDI (3.0)
 * Version 3.0
 * No changes

SMPTE2022-5/6 Video over IP Receiver (3.0)
 * Version 3.0 (Rev. 3)
 * Updated Demo test bench to support multiple channels

SMPTE2022-5/6 Video over IP Transmitter (3.0)
 * Version 3.0 (Rev. 3)
 * Updated Demo test bench to support multiple channels
 * Updated to handle random tready signal input to core, to comply with AXIS spec
 * Added two new registers in the channel register address space, to configure TOS/TOL in RTP and FEC packets

SPI-4.2 (13.0)
 * Version 13.0 (Rev. 3)
 * Repackaged to improve RTL simulation

SelectIO Interface Wizard (5.1)
 * Version 5.1
 * No changes

Serial RapidIO Gen2 (3.1)
 * Version 3.1
 * Increased the number of optional transceiver control and status ports.

Soft Error Mitigation (4.0)
 * Version 4.0 (Rev. 3)
 * This version of the IP does not yet support new Artix devices 7A35T and 7A50T.

System Cache (3.0)
 * Version 3.0 (Rev. 3)
 * Reduced warnings in synthesis and simulation

System Management Wizard (1.0)
 * Version 1.0
 * Initial release

Ten Gigabit Ethernet MAC (13.0)
 * Version 13.0 (Rev. 1)
 * Tidied up XDC syntax to use more specific endpoints for some constraints.
 * Unencrypted core source files are now delivered into the correct library.
 * Out-of-context XDC file now delivered into synth subdirectory.
 * Version register now returns the correct value.

Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) (4.1)
 * Version 4.1
 * Minor up-version because new optional transceiver debug ports are added
 * All port changes are documented in the core Product Guide PG068.
 * Connected signal_detect input to GTRXRESET in BASER configuration
 * Fixed PRBS31 enabling on GTHE3
 * Fixed 125us Timer setting in Example Designs for cores with no MDIO interface (AR58069)
 * Reinstated details in GUI of what logic will be shared when Shared Logic is selected
 * Merged the BaseR-only and the general transceiver debug interfaces in schematic component view
 * Kintex UltraScale Pre-Production support
 * Reinstated master reset usage on other resets in shared clock and reset block (VHDL only) (AR58498)

Test Pattern Generator (5.0)
 * Version 5.0 (Rev. 3)
 * Kintex UltraScale Pre-Production

Timer Sync 1588 (1.1)
 * Version 1.1 (Rev. 1)
 * No changes

Tri Mode Ethernet MAC (8.1)
 * Version 8.1
 * Kintex UltraScale Pre-Production support.
 * Full support for Synopsys VCS simulator.
 * Refactored the encrypted HDL to remove a level of design hierarchy and updated all core level XDC constraints where appropriate.  Most customer designs will not be creating XDC constraints which target logic within this core and so will be unaffected by this change.
 * Removed all generic parameters that passed through the readable HDL hierarchy of the core.  Generic parameters now only appear on the instantiation of the top level of the encrypted HDL portion of the core.
 * A new example design XDC file is provided to show customers how to override default XDC settings provided by the core itself for setup and hold timing adjustment of the selected physical interface.  This additional example XDC file is named <component_name>_user_phytiming.xdc
 * Added clock buffer information to the clocks defined in the out of context XDC file to support hierarchical design flows.
 * Added clock constraints for refclk, the IDELAYCTRL reference clock, to the out of context XDC for applicable permutations.

UltraScale FPGAs Transceivers Wizard (1.1)
 * Version 1.1
 * Added several new transceiver configuration preset options
 * Added support for the user data width sizing helper block
 * Added recovered clock output options in the Physical Resources tab
 * Added initial support for simulation of the CAUI-4 preset utilizing GTY transceivers

UltraScale FPGA Gen3 Integrated Block for PCI Express (2.0)
 * Version 2.0
 * Enabled all EP configurations
 * Enabled Advanced Mode
 * Enabled Xilinx Development Board and added option "KCU105"
 * RP simulation model in the test bench support only for x8Gen3 configuration
 * Removed support for 8KB COMPLETION_SPACE ("good mode") and kept 16KB COMPLETION_SPACE ("extreme mode") as default
 * Updated RAMB constraints to reflect changes made to COMPLETION_SPACE support
 * Changed Silicon Revision to 'ES1'
 * Added "-1 -c" parts and changed all part names to "-es1" from "-ies"

VIO (Virtual Input/Output) (3.0)
 * Version 3.0 (Rev. 1)
 * Kintex UltraScale Pre-Production support

Video Deinterlacer (4.0)
 * Version 4.0 (Rev. 3)
 * Added support for Automotive Zynq devices

Video In to AXI4-Stream (3.0)
 * Version 3.0 (Rev. 3)
 * Kintex UltraScale Pre-Production support
 * Automotive Zynq support

Video On Screen Display (6.0)
 * Version 6.0 (Rev. 3)
 * Repackaged to improve internal automation, no functional changes
 * Added Kintex UltraScale Pre-Production support
 * Added Automotive Zynq-7000 Production support

Video Scaler (8.1)
 * Version 8.1 (Rev. 2)
 * Kintex UltraScale Pre-Production support
 * Added automatic coefficient generation ability to the C Model
 * Added 4:4:4 RGB as a valid input in IPI

Video Timing Controller (6.1)
 * Version 6.1
 * Added support for interlaced video
 * Repackaged to improve internal automation
 * Added Kintex UltraScale Pre-Production support
 * Added Automotive Zynq-7000 Production support

Video to SDI TX Bridge (1.0)
 * Version 1.0 (Rev. 1)
 * Changed DUT instance name in testbench

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (3.0)
 * Version 3.0
 * Added port level enablement for icap and startup signal interfaces
 * Updated PIO TX_USERAPP module Device Control Register offset from 'h60 to 'hC8
 * Added 3 new ports - pipe_rxstatus, pipe_eyescandataerror and pipe_dmonitordout to the transceiver debug interface
 * Added input port cfg_subsys_vend_id to provide access to Subsystem Vendor ID
 * Added logic to power down CPLL until it is required during the PCIe link bring-up
 * Added component name as prefix in the core top level file
 * Changed the default value of BRAM Configuration Option to "Extreme/16KB" from "Good/8KB" (Xilinx Answer 58071)

Viterbi Decoder (9.0)
 * Version 9.0 (Rev. 3)
 * GUI tooltips added.
 * Support for Kintex UltraScale devices at Pre-Production Status

XADC Wizard (3.0)
 * Version 3.0 (Rev. 2)
 * No changes

XAUI (12.1)
 * Version 12.1
 * Added support for UltraScale
 * Increased the number of optional transceiver control and status ports.

YCrCb to RGB Color-Space Converter (7.1)
 * Version 7.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

ZYNQ7 Processing System (5.3)
 * Version 5.3 (Rev. 1)
 * DDRIOB_SLEW registers added in ps7_init
 * Removed toggling of FPGA_RST_CTRL register from post_config
 * Trace enabled for different port size such as  2,4,8,16 and 32 bits

ZYNQ7 Processing System BFM (2.0)
 * Version 2.0 (Rev. 1)
 * Repackaged files for IP Integrator to use the recommended file type: no functional changes

interrupt_controller (3.0)
 * Version 3.0
 * No changes
AR# 58670
Date Created 12/04/2013
Last Updated 12/20/2013
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.4