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AR# 58697

UltraScale/UltraScale+ Integrated Interlaken Core - IP Release Notes and Known Issues for Vivado 2013.4 and Forward


This answer record contains the Release Notes and Known Issues for the LogiCORE UltraScale Integrated Interlaken core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.4 and forward.

LogiCORE UltraScale Interlaken core IP Page:



General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Core VersionVivado Tools Version
v1.4 (Rev. 1)2014.4.1

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE UltraScale Interlaken core.

Table 2: General Guidance

Article NumberArticle Title
(Xilinx Answer 55248)Vivado Timing and IP constraints
(Xilinx Answer 61629)LogiCORE UltraScale Integrated Block for Interlaken - How do I speed up simulation?
(Xilinx Answer 62458)LogiCORE UltraScale Integrated Block for Interlaken - How do I generate a license key to activate this core?

Known and Resolved Issues
The following table provides known issues for the UltraScale Interlaken core, starting with v1.0, initially released in Vivado 2013.4

Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 3: IP
Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 67976)CDC-10 Critical Warning seen core_tx_reset, core_rx_reset, core_drp_resetv1.9NA
(Xilinx Answer 67975)Optional OOBFC RX input timing constraints are relaxedv1.9NA
(Xilinx Answer 64697) Timing failures using optional AXI-Lite management interface v1.5v1.6
(Xilinx Answer 64026)Optional OOBFC Interface - Difficulty meeting timing v1.4v1.7
(Xilinx Answer 63329)Invalid Reference Clock Distribution when Channels operating above 16.375 Gb/sv1.4v1.4 (Rev. 1)
(Xilinx Answer 61143)How do I generate UltraScale Integrated CMAC and Interlaken blocks in Vivado 2014.2?v1.2NA
(Xilinx Answer 60160)LogiCORE Interlaken v1.1 - 2014.1 Implementation results in timing errorsv1.1v1.2
(Xilinx Answer 58862)Simulation support is restricted to QuestaSim 10.2av1.0v1.1
(Xilinx Answer 58863)Support is restricted to Simulation-onlyv1.0v1.1
(Xilinx Answer 58864)Interlaken configuration is restricted to 12x12.5Gbps using GTH transceiversv1.0v1.1

Revision History:

12/18/2013Initial Release

Linked Answer Records

Child Answer Records

AR# 58697
Date 10/13/2016
Status Active
Type Release Notes
  • Kintex UltraScale
  • Virtex UltraScale
  • UltraScale - Interlaken