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AR# 58723

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 - PIPE Simulation does not work with 250 MHz Reference Clock

Description

Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 54645)

If simulating the example design for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 core generated with 250 MHz reference clock and PIPE simulation enabled, the simulation stops after the following message:

"System Reset is De-asserted...".

Solution

This is a known issue to be fixed in a future release of the core.

To work around this issue, replace the generated files with the ones attached at the end of this answer record.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
12/09/2013 - Initial release

Attachments

Associated Attachments

Name File Size File Type
pcie3_7x_0_gt_top_pipe.v 35 KB V
pcie3_7x_v2_2_pcie_3_0_7vx.v 233 KB V

Linked Answer Records

Master Answer Records

AR# 58723
Date Created 12/09/2013
Last Updated 12/09/2013
Status Active
Type Known Issues
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)