There is typically a paragraph in the device data sheet that precedes the "SelectIO DC Input and Output Levels" table that states: "... Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points..."
The VOL and VOH values provide the test-point voltages are that are used for specifying the IOL and IOH currents. Essentially, it specifies the minimum current drive across process, voltage, and temperature variation (PVT), at those test-point voltages.
To analyze the actual voltage levels that are reached when driving, it is important to consider if the SelectIO output buffer is toggling or only driving a steady DC level, as well as what is being driven on the PCB net. When the SelectIO output buffers are driving out with no resistive loads at a steady (DC) level, or only occasionally switching, the nets will tend to drive all the way to ground when low or all the way to VCCO when high. Resistive terminated loads will reduce the amplitude, for both non-toggling (DC) as well as toggling (AC) drivers. And when the buffer is toggling, as the data/toggle rates or the capitive loading on the nets go up, the signal amplitude will reduce.
The best way to analyze if a receiver's input requirements are being met by the Xilinx SelectIO output for DC or AC cases is to setup and perform signal integrity simulations (SI) using Xilinx's IBIS or HSPICE models, and models for any connectors and other devices on the PCB net. The Xilinx SI models, both HSPICE and IBIS, are available on the Xilinx Support website.