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AR# 58828

Vivado Design Suite 2013.4 - "LUTLP-1#1 Critical Warning Combinatorial Loop 2 LUT cells form a combinatorial loop. Modify the design to eliminate this unroutable situation..."

Description

The following warning occurs:.

LUTLP-1#1 Critical Warning
Combinatorial Loop
2 LUT cells form a combinatorial loop. Modify the design to eliminate this unroutable situation. topGN/LUT5_61, topGN/LUT5_62.

What is a combinatorial loop and is it really a problem?

My design passes bitstream generation, does that mean that I can ignore the problem?

Solution

A combinational loop is combinational logic that feeds back to itself without a register. The simplest example is an inverter whose output feeds back to the input creating an oscillator.

This DRC issue does need to be addressed and beginning with Vivado 2014.1, bitstream generation will not be allowed with this condition unless the message severity is overridden. The message has also been improved for 2014.1 to describe the issue more completely:

LUTLP-1#2 Critical Warning 
Combinatorial Loop
2 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. topGN/LUT5_38, topGN/LUT5_39.
Related violations: <none>
AR# 58828
Date Created 12/16/2013
Last Updated 12/16/2013
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite