The 10G AXI Ethernet core has several known issues that will be addressed in the 10G AXI Ethernet v1.2 core:
1) Issues fixed in the transmitter UDP checksum update logic.
2) Issues fixed in the transmitter 1-step timestamp insertion logic.
3) An issue has been fixed in the receiver timestamping logic where the top 16-bits of
the seconds field were held at zero.
4) XDC constraints around the handling of clock domain crossings in the
receiver timestamping logic have been fixed.