We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58831

10G AXI Ethernet v1.1 - Issues seen with timestamping and UDP checksum


The 10G AXI Ethernet core has several known issues that will be addressed in the 10G AXI Ethernet v1.2 core:

      1) Issues fixed in the transmitter UDP checksum update logic.

      2) Issues fixed in the transmitter 1-step timestamp insertion logic.

      3) An issue has been fixed in the receiver timestamping logic where the top 16-bits of the seconds field were held at zero.

      4) XDC constraints around the handling of clock domain crossings in the receiver timestamping logic have been fixed.


Please update to the 10G AXI Ethernet v1.2 core in 2014.1 or later.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
57358 AXI 10G Ethernet Subsystem - Release Notes and Known Issues for Vivado 2013.3 and newer tool versions N/A N/A
AR# 58831
Date 06/05/2014
Status Active
Type General Article
  • AXI 10 Gigabit Ethernet
Page Bookmarked