We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58836

2013.3 Vivado Sysgen - Blackbox block failing behavioral simulation with Data Mismatches for both VHDL and Verilog


ModelSim Blackbox failing behavioral simulation with Data Mismatches for both VHDL and Verilog.

When BlackBox block is simulated with External Simulator (i.e., ModelSim), then incorrect output results are generated in Sysgen simulation.
When SysGen generated netlist is simulated in Vivado, then mismatch is reported between expected output and Vivado simulator results.

Is this a known issue in Vivado Sysgen, and is there a possible work-around?


This happens if Default Radix for ModelSim is set to any value other than binary. This can be set in the modelsim.ini file.

It was found that the Default Radix = hexadecimal was set. When the default radix value was changed to binary, the mismatch issue was resolved.

Another work-around is to not use ModelSim and use built-in Vivado Simulator to simulate the Sysgen design.

A CR has been filed for this to be fixed in a future software release.

AR# 58836
Date 06/05/2014
Status Active
Type General Article
  • System Generator for DSP
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4