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AR# 58847

14.x ISE Sysgen - The Sysgen block AXI FIFO appears to be using block RAM resources when configured as Distributed RAM


In my Sysgen model, I have added an AXI FIFO block and configured it as a Distributed RAM, however, after generating and implementing the model, I can see that the FIFO was created using block RAM.

Is this a known issue? If so, how can I work around this problem?


This is a known issue in ISE Sysgen 14.5, 14.6, and 14.7. The problem is that the XCO file being generated from Sysgen and passed to the CORE Generator tool to generate the AXI FIFO contains incorrect parameter names which lead to the incorrect configuration being generated.

This is fixed in Vivado Sysgen and the work-around is to move to Vivado Sysgen where possible.

If you need to remain in ISE Sysgen, the options are to generate the FIFO Generator IP directly in the CORE Generator tool and bring this into your Sysgen model using the Black Box block in the Xilinx Blockset.

AR# 58847
Date 12/17/2013
Status Active
Type General Article
  • System Generator for DSP - 14.5
  • System Generator for DSP - 14.6
  • System Generator for DSP - 14.7
  • FIFO Generator