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AR# 58852

2014.2 Vivado Packager - Packaging an IPI block design with MIG core does not copy 'mig_a.prj' file to second IPI block design


There is an issue when you create an IPI block design with a MIG core and then package this BD to be added to another IPI block design.
The 'mig_a.prj' file is not copied from the initial design to the new design and the following error is seen when "Generate Output Products" is run.

ERROR: [IP_Flow 19-3460] Validation failed on parameter 'XML_INPUT_FILE(XML_INPUT_FILE)' for Specified PRJ file does not exist 'C:/cases/case992379/tests/project_1/project_1.srcs/sources_1/bd/design_2/ip/design_2_design_1_0_0/ip/design_1_mig_7series_0_0/mig_a.prj'
. IP 'design_1_mig_7series_0_0'

This same issue can also manifest itself with the error below:

[xilinx.com:ip:mig_7series:2.1-0] design_1_mig_7series_0_0: Code generation aborted: Can not read PRJ file: /group/xircss/ambrosef/CASE_1018917/test_2014_3/new_ip_test/project_1/project_1.srcs/sources_1/ip/design_1_0/ip/design_1_mig_7series_0_0/mig_a.prj
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'design_1_mig_7series_0_0'. Failed to generate 'Synthesis' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed.



The workaround is to copy the mig_a.prj file to the location specified in the errors.

For example: /project_1/project_1.srcs/sources_1/bd/design_2/ip/design_2_design_1_0_0/ip/design_1_mig_7series_0_0/mig_a.prj

If the MIG in the BD is multi-controller then there will be more than one mig_#.prj file and so the error will occur for them all. 

Copy all of the files as needed.

This issue is fixed in Vivado 2014.3.

AR# 58852
Date 09/19/2014
Status Active
Type General Article
  • SoC
  • FPGA Device Families
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
  • Memory Interface and Storage Element
  • MIG
  • MIG 7 Series
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