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AR# 58884

Xilinx Simulation Solution Center - Design Assistant - IP Simulation

Description

This Answer Record contains child answer records covering IP simulation issues. The answer records provides explanation of these issues which you may face while performing IP Simulation. The answer record also contains information related to known issues and good coding practices.

Note: This article is part of Xilinx Simulation Solution Center Xilinx Answer 58795. The Xilinx Simulation Solution Center is available to address all questions related to Simulation. Whether you are starting a new design with Vivado Simulator or troubleshooting a problem with a supported third party simulator, use the Xilinx Simulation Solution Center to guide you to the right information.

Solution

IP Simulation Model Queries

(Xilinx Answer 56700) 2013.2 Vivado IP Simulation - Error: [VRFC 10-950] instantiating from unknown module [tb.v 156]
(Xilinx Answer 60438) Vivado 2014.1 : How do I migrate IP created in a prior version of Vivado into the current release of Vivado
(Xilinx Answer 62498) 2014.3 - Ultrascale Simulation issues with IP Cores containing the GTH/GTY/PCIE primitives
(Xilinx Answer 62254) Zynq BFM simulation - Invalid release of reset.
 

Get Simulation Files

(Xilinx Answer 56491) How do I generate a simulation netlist file list in Vivado 2013.2 when using a managed IP project? 

(Xilinx Answer 59600) Vivado Simulator FAQ - How do I Collect simulation files from TCL console?

Common Error/Issues with IP Simulation

(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 60949) 2014.2 - Zynq BFM example design fails simulation in VCS and IES
(Xilinx Answer 60986) Artix-7/Kintex-7/Virtex-7 7-Series Integrated Block Wrapper for PCI Express v3.0 - Example Design fails simulation in 3rd party simulator when using pre-compiled libraries that are compiled in project mode
(Xilinx Answer 62341) FIFO Generator 12.0 - Failing to simulate using Modelsim/QuestaSim and producing errors associated to protected regions 
(Xilinx Answer 62583) 2014.x Vivado Simulator - xelab rangecheck may cause some IP cores elaboration failure due to too strict in handling VHDL null vectors
(Xilinx Answer 63224) Vivado simulator - Error "[VRFC 10-454] cannot open vhdl file" may occur in Windows OS when running behavioral simulation on IP Example Design 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58796 Xilinx Simulation Solution Center - Design Assistant N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
62254 Zynq BFM simulation - Invalid release of reset. N/A N/A
62498 2014.3 - Ultrascale Simulation issues with IP Cores containing the GTH/GTY/PCIE primitives N/A N/A
59600 Vivado Simulator FAQ - How do I Collect simulation files from TCL console? N/A N/A
60438 Vivado 2014.1 : How do I migrate IP created in a prior version of Vivado into the current release of Vivado N/A N/A
50909 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? N/A N/A
56700 2013.2 Vivado IP Simulation - Error: [VRFC 10-950] instantiating from unknown module [tb.v 156] N/A N/A
62583 2014.x Vivado Simulator - xelab rangecheck may cause some IP cores to fail to elaborate by being too strict in handling VHDL null vectors N/A N/A
63224 Vivado simulator - Error "[VRFC 10-454] cannot open vhdl file" may occur in Windows OS when running behavioral simulation on IP Example Design N/A N/A
60986 Artix-7/Kintex-7/Virtex-7 - 7 Series Integrated Block Wrapper for PCI Express v3.0 - Example Design fails simulation in 3rd party simulator when using pre-compiled libraries that are compiled in project mode N/A N/A
60949 2014.2 - Zynq BFM example design fails simulation in VCS and IES N/A N/A
56491 How do I generate a simulation netlist file list in Vivado 2013.2 when using a managed IP project? N/A N/A
62341 FIFO Generator 12.0 - Failing to simulate using Modelsim/QuestaSim and producing errors associated to protected regions N/A N/A
AR# 58884
Date Created 12/18/2013
Last Updated 04/02/2015
Status Active
Type Solution Center
Tools
  • Vivado Design Suite