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AR# 59020

Zynq-7000 Example design – GIC FIQ test (Handing interrupt from PL as a FIQ interrupt)

Description

This example design tests for FIQ interrupt.

This example is designed to work with axi_timer in PL to cause an FIQ interrupt.
The interrupt from axi_timer is connected to IRQF2P[15]( IRQ ID91)
The processor only operates in secure state.
The interrupt is set as group 0 interrupt as secure interrupts, signaled as FIQ to processor.
Hardware/Software: Generated by Vivado 2013.4 and tested on ZC702 production board.
 
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill your needs.
Limited support is provided by Xilinx on these Example Designs.
Implementation Details
Design Type
PS & PL
SW Type
Standalone
CPUs
Single CPU
PS Features
GIC
PL Cores
AXI Timer
Boards/Tools
ZC702
Xilinx Tools Version
Vivado 2013.4
Other details
The interrupt from axi_timer is connect to IRQ ID91
Address Map
 
Base Address
Size
Bus Interface
axi_timer
0x42800000
64K
S_AXI
Files Provided
sourceme.tcl
 Vivado project
gic_fiq_test.c
source code
                                                                         Block Diagram
block.png

 

Solution

 
Step by Step Instructions:
 
  1. Reproduce the design by source sourceme.tcl in vivado 2013.4
  2. Create HDL wrapper/ Generate Bitstream
  3. Export Hardware for SDK
  4. In SDK, generate an empty application, import gic_fiq_example.c
  5. Program PL using the Bitstream generated by Vivado Design Suite
  6. Run the application
 
Expected Results
Interrupt information will be printed as below:
 
log.png



 

Attachments

Associated Attachments

Name File Size File Type
gic_fiq_test.c 10 KB C
sourceme.tcl 8 KB TCL
AR# 59020
Date Created 01/08/2014
Last Updated 11/25/2014
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2013.4
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit