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AR# 59021

2013.x Vivado Simulator - Using reverse range attribute causes fatal error


Slicing a std_logic_vector using another signal's "reverse_range" attribute results in a fatal error in Vivado Simulator.

FATAL_ERROR: FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover.
Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.


This is a Vivado simulator issue and is fixed in the 2014.1 release.

To work around the issue, manually specify the correct range.

For Example:

signal a: std_logic_vector (8 downto 0);
signal b : std_logic_vector (4 downto 0);
signal c : std_logic_vector (0 to 4);


b<= a (c'reverse_range) ;


b<= a(4 downto 0);

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 59021
Date 03/18/2015
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.1
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