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  3. AR# 59039: Virtex-7 HT FPGA GTZ Transceiver - BUFGCTRL and BUFG_LB locations and constraints

AR# 59039

Virtex-7 HT FPGA GTZ Transceiver - BUFGCTRL and BUFG_LB locations and constraints

Description

This answer record covers the BUFGCTRL and BUFG_LB locations and guidelines when using the Virtex-7 HT GTZ Transceivers.

Solution

For guidelines on BUFGCTRL locations for USRCLKs generated via Fabric PLLs/MMCMs, refer to the attached Microsoft Word and Excel documents.

For BUFG_LB locations for TXUSRCLK/TXOUTCLKs and RXUSRCLK/RXOUTCLKs, refer to the tables below. 


Please ensure in the Vivado tools that the correct BUFG_LB locations are used as per these tables.

This information will be added to the 7 Series GTZ Advance Specification User Guide (UG478).

Octal Outclk to USRCLK BUFG_LB Location constraint
North TXOUTCLK0 to TXUSRCLK0 BUFG_LB_X1Y0 or BUFG_LB_X1Y16
TXOUTCLK1 to TXUSRCLK1 BUFG_LB_X1Y4 or BUFG_LB_X1Y20
South TXOUTCLK0 to TXUSRCLK0 BUFG_LB_X3Y15
TXOUTCLK1 to TXUSRCLK1 BUFG_LB_X3Y11

 

 

Octal Outclk to USRCLK BUFG_LB Location constraint
North RXOUTCLK0 to RXUSRCLK0 BUFG_LB_X1Y12 or BUFG_LB_X1Y28
RXOUTCLK1 to RXUSRCLK1 BUFG_LB_X1Y2 or BUFG_LB_X1Y18
RXOUTCLK2 to RXUSRCLK2 BUFG_LB_X1Y6 or BUFG_LB_X1Y22
RXOUTCLK3 to RXUSRCLK3 BUFG_LB_X1Y10 or BUFG_LB_X1Y26
South RXOUTCLK0 to RXUSRCLK0 BUFG_LB_X3Y3
RXOUTCLK1 to RXUSRCLK1 BUFG_LB_X3Y13
RXOUTCLK2 to RXUSRCLK2 BUFG_LB_X3Y9
RXOUTCLK3 to RXUSRCLK3 BUFG_LB_X3Y5

Attachments

Associated Attachments

Name File Size File Type
GTZ_Clocking_guidelines_using_BUFGCTRL.docx 341 KB DOCX
BUFGCTRL_Locations.xlsx 17 KB XLSX
AR# 59039
Date 06/17/2014
Status Active
Type General Article
Devices
  • Virtex-7 HT