I am experiencing unroutability issues related to a clock net driven by an IBUFDS_GTE2.
The following can cause routing issues in a design:
1) If there is no GTXE2_COMMON instantiated in the design and the only way to reach the QPLLCLK pin on the GTXE2_CHANNEL is from the QPLLOUTCLK of a GTXE2_COMMON.
The design will try to drive QPLLCLK directly from the IBUFDS_GTE2 which is not valid usage.
2. If the IBUFDS_GTE2 is also driving the DRPCLK pin of a number of GTXE2_CHANNEL components directly (for example, six).
This sort of connection is not documented, but the IBUFDS_GTE2 can only reach the DRPCLK pin on components in the same clock region by routing thru a BUFHCE.
Because there are only four GTXE2_CHANNEL sites in each clock region, all six connections can not possibly be made.
3. If the IBUFDS_GTE2 is directly driving fabric FF loads of 1300+ for example, these would need to be placed in the same clock region to be feasibly routed.
| AR# 59064 | |
|---|---|
| Date | 03/30/2015 |
| Status | Active |
| Type | General Article |
| Devices | |
| Tools | |