We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59077

JESD204B - v2.2 - ISE - Only Address = 0 works in Example Test Bench


When trying to program the registers of JESD204B, Only an address = 0 will work.

It seems like an incorrect parameter is set in the RTL.
jesd204_v2_2_pselect_f.v. --> parameter [0:C_AB-1]BAR = C_BAR[0:C_AB-1];
BAR is always = 0; in Simulation,
1. C_AB is 0x7
2. C_AW is 0x7
3. CE_ADDR_SIZE = 0x7
4. C_BUS_AWIDTH = 0x9
5. TEMP_CE = 0x43

So, from the above parameters, when the address is 0x4, 0x8, 0xc,... It should have value when AValid = 1'b1, but it is not. How do I fix this?


To resolve this incorrect address, the following update should be made:

     --> wire [0:C_AB-1]BAR = C_BAR[0:C_AB-1];

This change helps the simulation to work and the registers of JESD204B can now be written and read to. 

This issue is only present in CoreGen ISE JESD204B designs and is not an issue with Vivado designs.

Revision History:
01/13/2014 - Initial Release 

AR# 59077
Date 04/25/2014
Status Active
Type General Article
  • JESD204