We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59089

XAPP589 - v2.1-When using the VCXO secondary clocking scheme, pre_opt_design.tcl errors out


When I use the VCXO secondary clocking scheme and run pre_opt_design.tcl, the following error occurs:

[Vivado 12-180] No cells matched 'get_cells -filter {PRIMITIVE_SUBGROUP == gt} -of [get_pins -leaf -filter {DIRECTION == OUT} -of [get_nets -of [get_pins -leaf -filter {DIRECTION == IN && IS_ENABLE == 0} -of [get_cells -of [get_pins -leaf -filter {DIRECTION == OUT} -of [get_nets -of [get_pins -of [get_cells teng_sidei/picxo_top_wrapper_teng/Inst_picxo_top] -filter {NAME =~ *txoutclk_i}]]]]]]]'.


The secondary clocking scheme is as follows:

This error is a known issue, please use the modified Tcl script attached to the end of this answer record (pre_opt_design.tcl).

This issue is fixed in v2.2.


Associated Attachments

Name File Size File Type
pre_opt_design.tcl 6 KB TCL

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56136 XAPP589 - XAPP1241 - All Digital VCXO Replacement (PICXO) - Design Assistant / Master Answer Record N/A N/A
AR# 59089
Date 07/24/2015
Status Active
Type General Article
  • Artix-7
  • Artix-7Q
  • Kintex-7
  • More
  • Kintex-7Q
  • Virtex-7
  • Virtex-7Q
  • Less
Page Bookmarked