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  3. AR# 59146: 2013.4 Vivado Power - Combinatoral Toggle rate appears incorrect vs. the Report_Power results

AR# 59146

2013.4 Vivado Power - Combinatoral Toggle rate appears incorrect vs. the Report_Power results

Description

The .xpe file generated from Vivado Report_Power contains the following:

<LOGIC clock="" clockFreq="101.152442" toggleRate="99.912975" name="Combinatorial" hierName="top" writeRate="0.000000" enableRate="0.000000" fanout="8.235109" numNets="161756" extNets="20029" BUFG="1" carry4s="4" luts="160931" logicCap="39621987738" signalCap="5903011.000000" power="2.003600">

The toggle rate reported in the Vivado Report_Power is between 49-50%. 

The clock frequencies match between report_power and .xpe file.

Why is this happening?

Solution

This is the desired behavior.

Because XPE computes the Signal Rate from Clock and Toggle Rate, we have to manufacture a clockFreq and toggleRate tag for Asynchronous logic in the .xpe file in order for the signal rates to match in report_power and XPE.

This is also done in other areas such as block RAMs and DSPs.
AR# 59146
Date 12/17/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.4

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