The .xpe file generated from Vivado Report_Power contains the following:
<LOGIC clock="" clockFreq="101.152442" toggleRate="99.912975" name="Combinatorial" hierName="top" writeRate="0.000000" enableRate="0.000000" fanout="8.235109" numNets="161756" extNets="20029" BUFG="1" carry4s="4" luts="160931" logicCap="39621987738" signalCap="5903011.000000" power="2.003600">
The toggle rate reported in the Vivado Report_Power is between 49-50%.
The clock frequencies match between report_power and .xpe file.
Why is this happening?
AR# 59146 | |
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Date | 12/17/2014 |
Status | Active |
Type | General Article |
Tools |