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AR# 59157

FPGA - Distributed RAM - General Advice when building distributed memory


What are the best practices to follow when building distributed memory?


Xilinx strongly suggest to avoid exceeding a depth that is naturally supported by CLB logic.

Wider memory is more natural than trying to make it deeper.

There are multiple options available for creating distributed RAM (for example through the wizard or inference)

In general it is best to have the distributed RAM available to be used at the primitive level where it is most efficient rather than to use more logic to join smaller memories together.

Below are examples with the depth not exceeding one CLB logic.

 K7 - Single-Port 256 x 1-bit RAM

 V6 - Single-Port 256 x 1-bit RAM

 V5 - Single-Port 256 x 1-bit RAM

AR# 59157
Date 06/19/2014
Status Active
Type General Article
  • Kintex-7
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