This is a list of required items, necessary actions, and points to be considered, when debugging QSPI programming and booting on Zynq-7000 SoC.
Before opening a Service Request, collect all of the information requested below.
See (Xilinx Answer 50991) to determine the support category (Supported, Limited Support or Unsupported).
Please provide the full flash name, the configuration type (single, dual parallel, dual stacked) and the voltage. If the configuration is not "standard" (muxes, level shifters or other), provide also the board schematics.
Use XMD to read and report the PS_VERSION from 0xF8007080.
Please provide Silicon Version reporting register 0xF8007080
Use XMD to try to connect to the CPU.
Please provide JTAG chain description (how many devices on the chain, how many Zynq, Zynq in cascade or independent JTAG, any level shifter in the chain). Report any XMD error.
If some printing comes out on the UART during boot:
Please provide a log of the FSBL print out on the UART. FSBL is a user application and can be easily debugged using SDK. Try to do a brief investigation before filing a Service Request.
- If nothing comes out on the UART during boot, first double check the UART baudrate.
Please provide the status of INIT_B (high or low or blinking), REBOOT_STATUS and BOOT_MODE registers after the boot failure.
Most likely the boot image was not programmed properly (continue to step 5).
Please provide the version of the tool used. Be sure your image was built with the same version of the tool used to program.
Please provide the boot mode settings used for programming (booting from JTAG or QSPI).
Please provide the log obtained using the XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES variable.
Use the u-boot.elf pre-built from the latest released image on the wiki, and follow the CTT guide (UG873) including the instructions under "Program QSPI Flash With the Boot Image Using JTAG and U-Boot Command".
Please provide the log of the programming using pre-built u-boot image from the wiki. Specify the u-boot version used.
Use u-boot and double check the clock settings to verify the QSPI clock frequency (QSPI_REF_CLK and QSPI_CLK on the CLK pin).
Remember that QSPI has two modes of operations depending on if the clock frequency is higher or lower than 40MHz. Calculate and verify the QSPI clock speed.
Please provide the register settings and the calculation done to verify the QSPI clock frequency.
Some Debugging is required to understand where the example is failing (through the SDK debugger or by adding debug prints).
Is the issue with the initial query of the QSPI or a mismatch between writes and reads?
Is there any error pattern in the read back data? (Maybe a particular bit stuck to 1 or 0).
Report the type of failure in the Xilinx standalone example