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AR# 59201

Vivado Timing - The "actual value" of Low/High Pulse Width given by report_pulse_width is smaller than the expected value in Synthesized Design


The pulse width actual value reported by report_pulse_width is smaller than the expected value in Synthesized design.

Below is an example, in which the pulse width actual value (0.994) is smaller than half of the period value (1.017).

However the value reported in the Implemented Design is as expected.

What is the problem?

report_pulse_width -significant_digits 3


Clock Name:        clk
Waveform:           { 0   1.017 }
Period:                 2.03
Sources:              { clk }

Check Type            Corner     Lib Pin                Reference Pin   Required     Actual  Slack             Location  Pin
Min Period                 n/a        BUFG/I                 n/a                     1.408         2.034   0.625            clk_IBUF_BUFG_inst/I
Low Pulse Width      Slow      RAMD64E/CLK    n/a                      0.768         0.994   0.226            U0/synth_options.dist_mem_inst/gen_dp_ram.dpram_inst/ram_reg_0_127_0_0/DP.HIGH/CLK
High Pulse Width     Slow      RAMD64E/CLK    n/a                      0.768         0.994   0.226            U0/synth_options.dist_mem_inst/gen_dp_ram.dpram_inst/ram_reg_0_127_0_0/DP.HIGH/CLK


This is expected behavior of the tool.

The Pulse width check in Synthesized design is conservative.

This check should be done in Implemented design for accurate results.

The timer computes the pulse width being checked using the open and close edge arrival times and the CRPR (Clock Re-convergence Pessimism Removal). 

For a given clock pin (supposing the duty cycle is 50%), the worst case high pulse width actual value is calculated in this way:

Worst case high pulse width = Close edge arrival time - Open edge arrival time - CRPR
In which
Open edge arrival time = max clock path delay
Close edge arrival time = min clock path delay + half period

The difference between the Synthesized design and the Implemented design comes from the CRPR calculation.

In Implemented design, the NCN (Nearest Common Node) CRPR calculation is able to recognize that the common clock path of the Close edge and Open edge are completely the same.

This is because the check is on the same clock pin.

The CRPR is calculated as below:

CRPR = min clock path delay - max clock path delay

So the worst case high pulse width is finally equal to half of the period. 

However, in the Synthesized design there is no support for NCN CRPR.

As a result the CRPR is under-estimated for the clock, and the high pulse width calculated in the synthesized design is smaller than half of the period (which is conservative).
AR# 59201
Date 08/22/2014
Status Active
Type Known Issues
  • Vivado Design Suite
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