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AR# 59228

2013.4 Vivado HLS - Example showing how to use logic debug to test an AXI Lite Slave and AXI Master interface, and then verify it in SDK.

Description

This design targets the ZC702 board. 

It uses one AXI LITE Slave port to control the operation of the HLS IP and one AXI Master port to read and write data.

It is verified by Vivado Logic Debug and SDK.

The steps to create are below:

Solution

1. Create a HLS project and run synthesis. 

Then verify it through RTL Co-simulation. 

The source code and directive is as follows:



2. Export the RTL as IP Catalog.

The Vivado HLS project is attached.

3. Create a Vivado project. 

Set the HLS IP in the IP Settings of IP Catalog in Vivado as follows:




3. Create an IPI design and mark debug the AXI interfaces as follows:


Set the addresses of the IPs in the IPI design as follows:


4. Run Synthesis in Vivado and then open the synthesized design.

Open the Debug window and click Tools->Set up Debug. 

Use FCLK_CLK0 of Zynq as the clock domain.
 

5. Generate the bitstream in Vivado and open the Implemented Design.
 

6. Choose File->Export->Export Hardware for SDK. 

Check "Include bitstream" and "Launch SDK" in the pop up window.
 

7. In SDK, set repositories for the driver of HLS IP by choosing Xilinx Tools -> Repositories, as follows:



8. Create one Board Support Package using the default configuration.
 

9. Open system.mss in the text editor and modify the "DRIVER_NAME" of the HLS IP from "generic" to "foo_top_top".

See (Xilinx Answer 58096) for more details.

 

10. Create an Application Project in SDK and choose "Hello World" as the template.

11. In SDK, choose Xilinx Tools -> Program FPGA to download the bit file.


12. Open Hardware Manager in Vivado. 

Select "open a new hardware target" to connect to the debug core. 

Choose all default settings in the pop-up window.
 
13. Set "design_1_i/foo_top_0_M_AXI_M_AWVALID" to "1" as the trigger condition, and then trigger the ILA core as follows:

14. In the XMD Console of SDK, type following commands to connect to the Zynq CPU:

connect arm hw

15. In the XMD Console of SDK, type the following command to set ap_start to 1:

mwr 0x43c00000 1

Type the following command to set "con" to 1:

mwr 0x43c00014 1

Type the following command to set "BASE_ADDR" to 0x40000000:

mwr 0x43c0001c 0x40000000

Type the following command to set control of "BASE_ADDR" to valid:

mwr 0x43c00018 1

Type the following command to set control of "con" to valid
 

mwr 0x43c00010 1

These addresses for HLS IP can be found in file "xfoo_top_hw.h".

Now the HLS IP will start operation and ILA is triggered. 

Check the captured waveform in Vivado.



16. Write the SDK application project using the HLS IP driver as follows:



17. Launch the application project in Hardware and observe that the memory output is expected:

This is the memory content before operating:
 
1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40
 
This is the memory content after operating:
 
2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 

Note that the output content depends on how many times the HLS IP has launched.

 

The Vivado project including SDK project is attached.

Attachments

Associated Attachments

Name File Size File Type
HLS_AXIM_LITE_test.zip 111 KB ZIP
AR# 59228
Date Created 01/26/2014
Last Updated 03/30/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.4