I have a Vivado project which includes DCP files for some Xilinx IP which were generated using the Manage IP flow and also includes DCP files generated from other HDL projects in Vivado.
When building the overall design in Vivado and linking the design, I received warnings which referenced the original XDC file location from the projects where these DCP files were created.
WARNING: [Constraints 18-402] set_max_delay: 'eth2_wrapper_i0/ge_mac/u_gig_eth_pcs_pma_lvds_v13_0/U0/lvds_transceiver_mw/tx_gearbox_i/accumulator_60b_reg_i_1' is not a valid startpoint.
Resolution: A valid start point is a main or generated clock pin or port, a clock pin of a sequential cell, or a primary input or inout port. Please validate that all the objects returned by your query belong to this list.
Is this expected?
Does the DCP contain all the necessary constraints, or do I need to include other files in the new project?
This is expected. The DCP should have all the information required for the IP. The constraints within the DCP will have XDEF references from the original constraint location.
For IPs, the only other files required are the wrapper file and the XCI file.