In Vivado 2013.4 there is no netlist generated for a Logic Debug core.
Why is this? How can one be generated?
No synthesized netlist is available for debug cores because inserting it at the netlist stage can complicate design timing.
If an ILA's netlist is required, Follow the steps below to produce one.
Please note that this flow is not supported or guaranteed to work by Xilinx.
1) Create a dummy project.
2) Create the ILA and set it as the top module.
3) Run this Tcl command:
synth_design -mode out of context
4) Run the command:
This will generate a DCP for the ILA only.
If step 3 above generates the error message "No HDL sources specified", try the following workaround:
1) Create a new "Manage IP" project in Vivado.
2) Select the "Add Existing IP" option to add the ILA create earlier to this design.
3) Run the Tcl commands from steps 3 and 4 above.