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AR# 59292

XAUI and RXAUI Vivado 2013.4 and earlier - TX Phase Alignment statemachine not reset on falling edge of powerdown

Description

When using XAUI v12.1 or RXAUI v4.1, TX Phase Alignment statemachine is not reset on the falling edge powerdown. 

This could result in link up failures when powerdown is released.

Solution

To fix this edit the <core_name>_block.v/vhd file on the txsync_i instantiation:

If using Verilog change from:

txsync_i
(
.STABLE_CLOCK (clk156),
.RESET_PHALIGNMENT (reset156),

to:


txsync_i
(
.STABLE_CLOCK (clk156),
.RESET_PHALIGNMENT (uclk_mgt_tx_reset),

If using VHDL change from:

  txsync_i : <core_name>_gt_wrapper_tx_sync_manual
        ...
        STABLE_CLOCK                    =>      clk156,
        RESET_PHALIGNMENT               =>      reset156,


to:

  txsync_i : <core_name>_gt_wrapper_tx_sync_manual
        ...
        STABLE_CLOCK                    =>      clk156,
        RESET_PHALIGNMENT               =>      uclk_mgt_tx_reset,

This has been fixed in XAUI v12.1 (Rev. 1) and RXAUI v4.2 released in Vivado 2014.1.

Linked Answer Records

Master Answer Records

AR# 59292
Date Created 01/31/2014
Last Updated 04/17/2014
Status Active
Type General Article