For CPLL based 7 Series GTX/GTH designs and PLL0/PLL1 based GTP designs (for the rest of this article, all such PLL instances will be referred to as CPLL), there can be a current spike on MGTAVTT immediately after configuration.
Each GT lane with CPLL enabled contributes to the current spike.
Following the current spike, bit errors might be seen on the receive data.
This behavior is correctable by asserting RXPMARESET or GTRXRESET.
The current spike on MGTAVTT might be seen when the CPLL is enabled before the reference clock has propagated to the CPLL.
It can take up to one ms to propagate the reference clock through the IBUFGDS_GTE2 to the CPLL.
To resolve this current spike issue, hold the CPLL in power down until the input reference clock is toggling.
This can be done by counting valid reference clock pulses while keeping CPLLPD asserted high.
This solution ensures CPLL is powered down until a reference clock is propagated to the CPLL; only then should the normal initialization sequence be initiated.
Starting from Vivado 2013.4, the PCIe core v3.0 powers down the CPLL until the reference clock is stable to resolve the current spike issue.
GTX/GTH wizard protocols except for PCIe in 2014.2 FPGA Transceiver Wizard V3.3 also have the fix included.
GTP wizard protocols will be updated in 2015.3.
Coding examples for the suggested fix are attached.
The suggested code fits in a single slice.
Impact to production designs: