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AR# 59294

Design Advisory GT wizard - CPLL causes power spike on power up for 7 series GTs

Description

For CPLL based 7 Series GTX/GTH designs and PLL0/PLL1 based GTP designs (for the rest of this article, all such PLL instances will be referred to as CPLL), there can be a current spike on MGTAVTT immediately after configuration.

Each GT lane with CPLL enabled contributes to the current spike.

Following the current spike, bit errors might be seen on the receive data.

This behavior is correctable by asserting RXPMARESET or GTRXRESET.

The current spike on MGTAVTT might be seen when the CPLL is enabled before the reference clock has propagated to the CPLL.

It can take up to one ms to propagate the reference clock through the IBUFGDS_GTE2 to the CPLL.

Solution

To resolve this current spike issue, hold the CPLL in power down until the input reference clock is toggling.

This can be done by counting valid reference clock pulses while keeping CPLLPD asserted high.

This solution ensures CPLL is powered down until a reference clock is propagated to the CPLL; only then should the normal initialization sequence be initiated.

Starting from Vivado 2013.4, the PCIe core v3.0 powers down the CPLL until the reference clock is stable to resolve the current spike issue.

GTX/GTH wizard protocols except for PCIe in 2014.2 FPGA Transceiver Wizard V3.3 also have the fix included.

GTP wizard protocols will be updated in 2015.3.

Coding examples for the suggested fix are attached.

The suggested code fits in a single slice.


Impact to production designs:

  • This issue occurs only during the initial power-up.

  • There has been no reported functional failure for a system that passed the initial system level testing but started failing afterwards.

  • All of the reported functional failures are related to PCIe protocols, although functional issues are possible in some other protocols.

  • Protocols such as XAUI, CPRI and JESD have auto recovery which should recover from any problem.
    Other protocols such as Serial Rapid I/O avoid any possible functional issues because the Transceiver is being held in reset during the power spike.

  • Xilinx recommends updating designs but not recalling boards that have been shipped.

Attachments

Associated Attachments

Name File Size File Type
GTXFix.v 3 KB V
GTHFix.v 3 KB V
GTPFix12.v 3 KB V

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 59294
Date Created 01/31/2014
Last Updated 07/31/2015
Status Active
Type Design Advisory
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7