UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59391

Simulation: NCSim stops simulation with the error message: ncelab: *E,​MULVLG: Possible bindings for instance of design unit xxx_unit_name_xxx

Description

When running a simulation with NCSim I receive the below error message:

ncelab: *E,MULVLG: Possible bindings for instance of design unit '<xxxx>' in '<lib_name>.<module_name>:v' are:
        simprims_ver.<xxxx>:module
        unisims_ver.<xxxx>:module


What does this error mean and how can I resolve it?

Solution

This error is due to a full binding not being found in elaboration.

 

If the instance in question is a Verilog module, ensure that you specify the correct pre-compiled library for simulation.

The Vivado simprims_ver library uses the same source as unisims_ver with the addition of specific blocks for timing annotation. 

As a result, the Verilog simulation models share the same name in both simprims_ver and unisims_ver.

 

For functional simulation, specify the unisims_ver library with the ncelab command. 

For timing simulation, specify the simprims_ver library with the ncelab command. 

Please refer to the IES documentation for the correct command line switch to point to the pre-compiled libraries.

 

If the instance in question is a VHDL library component, try to add the "-relax" switch to the ncelab command.

 

The ncelab -relax option can be used to relax the strict default binding search order. 

The search order used with -relax will also search for a design unit in a library defined in the cds.lib file. 

That is, if a binding has not been found, the elaborator opens the cds.lib file and searches all of the libraries that are defined in the file that have not already been searched. 

 

Starting from Vivado 2014.3, IES is fully integrated into the Vivado IDE and unified simulation flow is introduced. 

We recommend that you either launch IES simulation from Vivado IDE, or use the simulation script generated by Vivado to run simulation in stand-alone IES.

For more details, please refer to (UG900) Vivado Design Suite User Guide: Logic Simulation.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58890 Xilinx Simulation Solution Center - Design Assistant - Third Party Simulators - Cadence IES N/A N/A

Associated Answer Records

AR# 59391
Date Created 02/12/2014
Last Updated 04/15/2015
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite