The Zynq processing system FCLK(x) does not run unless some registers in the Processing System (PS) are modified.
This means that the design in the Programming Layer (PL) will not operate until this is done.
This will affect any connection to the PL design with Debug Cores/ ILA/VIA/JTAG.
As soon as the hardware is programmed the following error might appear:
ERROR: [Labtools 27-1437] Failed to get a response from the Debug Core Hub on device XC7Z020_1 (JTAG device index = 1), in user chain = 1.
1) Verify that the clock signal connected to the debug core is clean and free-running.
2) Verify that the clock connected to the debug core meets all timing constraints.
It is important to use SDK to program the Zynq PL when the dbg_hub cores XSDB_CLK clock input is connected to the PS7s FCLK_CLK0 output.
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