AR# 59476


Zynq-7000 SoC: SD Programming/Booting Checklist


This is a list of required items, necessary actions, and points to be considered, while debugging SD booting on Zynq-7000 SoC.


Before opening a Service Request, collect all of the information requested below:.

1) SD booting.

SD booting is supported by Xilinx.

See (Xilinx Answer 50991) to determine the benefits and downsides of SD booting.

Please provide the board schematics and the name of the SD Memory Card used.

2) Is Zynq Production Silicon?

- Use XMD to read and report the PS_VERSION from 0xF8007080.

The following are known issues related to SD booting on GES :

(Xilinx Answer 52023) SD card controller does not wait 74 clock cycles to issue CMD0
(Xilinx Answer 52016) SDIO boot mode inadvertently uses Card Detect on MIO pin 0
(Xilinx Answer 51907) SDIO Boot runs at low frequency and data width.

Please Provide Silicon Version reporting register 0xF8007080


3) In which phase of booting is Zynq is failing? BootROM or FSBL?

In order to determine this, program an image with FSBL debug prints enabled.

#define FSBL_DEBUG_INFO in fsbl_debug.h

If some printing comes out on the UART during boot,

Please Provide a log of the FSBL print out on the UART.

FSBL is a user application and can be easily debugged using SDK.


This should be attempted before filing a Service Request.

- If nothing comes out on the UART during boot, first double check the UART baudrate.


Please provide the status of INIT_B (high or low or blinking), REBOOT_STATUS and BOOT_MODE registers after the boot failure.

4) Are SD_CD and SD_WP properly connected on the board?

Please provide ps7_init.tcl to verify SD_CD and SD_WP are properly configured to be directed to MIO or EMIO (depending on the board schematics).

5) Is  the SD running at a supported frequency?

- Check the SD clock configuration. See (UG585) chapter 25 about Clocks.

Please provide the register settings and the calculation done to verify the SD clock frequency.

6) Is the JTAG chain operating properly?

- Use XMD to attempt to connect to the CPU.

Please provide JTAG chain description (how many devices on the chain, how many Zynq, Zynq in cascade or independent JTAG, any level shifter in the chain).

Report any XMD error.

7) Is the Xilinx standalone example working?

Some Debugging is required to understand where the example is failing (Through the SDK debugger or by adding debug prints).

Report the type of failure found in the Xilinx standalone example.

AR# 59476
Date 05/28/2018
Status Active
Type General Article
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