(UG949), in the section "Overlapping Clocks Driven by a Clock Multiplexer" provides two methods to apply the clock group constraints in two different use cases.
However, I have a scenario involving cascaded BUFGMUX.
Take the following clocking structure as an example:
Suppose the use case falls to the second case in (UG949), where the input clock(s) directly interact with the multiplexed clock.
At POINT1, I define 2 generated clocks, clka (driven by clk1) and clkb (driven by clk2).
I also define clkc/clkd at POINT2.
Since all clocks (a/b/c/d) can propagate to BUFGMUX3, how do I constrain the clock at POINT3?