AR# 59484


Vivado - Constraint methodology for clock driven by cascaded BUFGMUX


(UG949), in the section "Overlapping Clocks Driven by a Clock Multiplexer" provides two methods to apply the clock group constraints in two different use cases.

However, I have a scenario involving cascaded BUFGMUX.

Take the following clocking structure as an example:

                Clk1 ----
                                |---- BUFGMUX1 ---- POINT1 ----
                Clk2 ----                                                                |
                                                                                                |---- BUFGMUX3 ---- POINT3
                Clk3 ----                                                                |
                                |---- BUFGMUX2 ---- POINT2 ----
                Clk4 ----

Suppose the use case falls to the second case in (UG949), where the input clock(s) directly interact with the multiplexed clock.

At POINT1, I define 2 generated clocks, clka (driven by clk1) and clkb (driven by clk2). 

I also define clkc/clkd at POINT2.

Since all clocks (a/b/c/d) can propagate to BUFGMUX3, how do I constrain the clock at POINT3?





You will need to define 4 generated clocks on POINT3: 2 for clka/clkb and 2 for clkc/clkd.

Please refer to the following syntax example.

create_generated_clock -name clk1mux -divide_by 1 -add -master_clock clk1 -source [get_pins BUFGMUX_inst1/I0] [get_pins BUFGMUX_inst1/O]
create_generated_clock -name clk2mux -divide_by 1 -add -master_clock clk2 -source [get_pins BUFGMUX_inst1/I1] [get_pins BUFGMUX_inst1/O]
set_clock_groups -physically_exclusive -group clk1mux -group clk2mux
create_generated_clock -name clk3mux -divide_by 1 -add -master_clock clk3 -source [get_pins BUFGMUX_inst2/I0] [get_pins BUFGMUX_inst2/O]
create_generated_clock -name clk4mux -divide_by 1 -add -master_clock clk4 -source [get_pins BUFGMUX_inst2/I1] [get_pins BUFGMUX_inst2/O]
set_clock_groups -physically_exclusive -group clk3mux -group clk4mux
create_generated_clock -name clk1mux_cas -divide_by 1 -add -master_clock clk1mux -source [get_pins BUFGMUX_inst3/I0] [get_pins BUFGMUX_inst3/O]
create_generated_clock -name clk2mux_cas -divide_by 1 -add -master_clock clk2mux -source [get_pins BUFGMUX_inst3/I0] [get_pins BUFGMUX_inst3/O]
create_generated_clock -name clk3mux_cas -divide_by 1 -add -master_clock clk3mux -source [get_pins BUFGMUX_inst3/I1] [get_pins BUFGMUX_inst3/O]
create_generated_clock -name clk4mux_cas -divide_by 1 -add -master_clock clk4mux -source [get_pins BUFGMUX_inst3/I1] [get_pins BUFGMUX_inst3/O]
set_clock_groups -physically_exclusive -group clk1mux_cas -group clk2mux_cas -group clk3mux_cas -group clk4mux_cas

AR# 59484
Date 12/17/2014
Status Active
Type General Article
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