In my top-level VHDL file I have two generics:
my_std_logic_vector: STD_LOGIC_VECTOR (3 downto 0) := "1111";
my_unsigned: UNSIGNED (3 downto 0) := "1010");
It looks like the both of the generics are successfully processed by the IP Packager.
When the packaged IP is imported into the IP Catalog of the final design, the IP GUI represents information in a correct way.
However, when I click OK to generate the IP I receive an error from Vivado saying that it is not possible to generate the IP:
ERROR: [Common 17-39] generate_target failed due to earlier errors.
In the message window there are several messages similar to the following:
[IP_Flow 19-152] Failed to convert bitString value '"1010"' to HDL value.
In the generated wrapper ( my_adder_0.vhd ) there is no value for my_unsigned in the generic map.
U0 : my_adder
GENERIC MAP (
width => 8,
rst_enable => true,
my_std_logic_vector => B"1111",
This issue is seen with both UNSIGNED and SIGNED generics.