Attached is the C++ design for a HLS AXI DMA (configurable for either GP or HP Zynq interfaces).
The design creates a ping pong buffer (via #pragma HLS DATAFLOW) of user defined length & width.
A C++ test bench is included.
The advantages are reduced size (compared to AXI Datamover, AXI VDMA) and simplification (no software programming is required to start using).
Another advantage is a user configurable processor interrupt that notifies the Cortex A9 after x words of data have been transferred (to allow the processor to start processing the data while data is still being moved).