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AR# 59534

Changing the Cacheability of Memory For Zynq in the Xilinx SDK

Description

This article summarizes how to change the cacheability of memory using the standalone BSP in the Xilinx SDK.

Solution

See the attached document.

Attachments

Associated Attachments

Name File Size File Type
Changing The Cacheability for Memory 379 KB PDF
AR# 59534
Date Created 02/25/2014
Last Updated 03/25/2015
Status Active
Type General Article
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q
Tools
  • Vivado Design Suite - 2013.4