When running simulations of Xilinx IP core, some files can be compiled into the "work" library by default, why is this?
Will this be changed in the future?
Starting with Vivado 2014.1, "work" is no longer used as a working library for Xilinx IP.
Instead, a work library called xil_defaultlib is used.
The background and motivations behind this change are below:
In VHDL there is no library named WORK. Instead, the identifier WORK just refers to the current library.
As per Section 11.2 (LRM 1076-2000) you can read the following:
Every design unit [...] is assumed to contain the following implicit context items [...]
library STD, WORK; use STD.STANDARD.all; [...]
Library logical name *WORK denotes the current working library* during a given analysis.
By default we will be strictly following the VHDL LRM and any usage of logical library "work" will always refer to the current working library.
If a library is specified for instantiation, we will only use that library
Motivations for change: