This update procedure is applied only when the line rate and reference clock selections fall under the RX reset Sequence requirements mentioned in (Xilinx Answer 53779)
Generate the GT Wizard wrapper as described in PG066.
Modify the instantiation of the GT Wizard in the file <corename>_gtwizard_top.v provided with the JESD204 IP (not the version provided with the GT Wizard) by adding the following additional signals:
Note: Leave outputs as open and connect rst_in to system reset.
.rst_in(Connect to System Reset),
Add the extra module's jesd204_gtwizard_0_gtrxreset_seq and jesd204_0_gtwizard_0_sync_block to the project.
You should generate the Core with the option "Include shared logic in example design" selected and then include the Transceiver and these extra modules in the project.
This will ensure that these modules are added to the project correctly.
Note: If you instead generate the Core with the "Include shared logic in core" option the extra modules won't be detected even if they are added to the project.
Follow the remaining steps mentioned in PG066.
For simulation of the generated test bench to pass successfully you need to change the core clock (line rate/40), reference clock and line rate parameter UI to the correct values matching the modified reference clock and line rate.
04/24/14 - Initial Release