Most Xilinx IP deliver behavioral simulation models for a single language only, effectively disabling simulation for language-locked simulators if you are not licensed for the appropriate language.
For cases in which a behavioral model is missing or does not match the licensed simulation language, the Vivado tools automatically generate a structural simulation model to enable simulation.
Otherwise, the existing behavioral simulation model for the IP will be used.
The table below illustrates the function of the simulator_language property.
To know what models are delivered by the IP, kindly refer to the IP Data Sheet.
You can set simulator_language while creating your project in Vivado and also under Project Options > Simulation as displayed below:
New Project Window
Project Settings > Simulation
For TCL it can be set as a property. For example:
set_property simulator_language VHDL [current_project]
- If no synthesis or simulation files exist, simulation is not supported.
- Where available, Behavioral Simulation will always take precedence and be advertised over Structural Simulation.
You will not be offered a choice of simulation mode.
- The simulator_language property will not be able to deliver netlist simulation files if the Generated Synthesized Checkpoint (.dcp) option is unchecked when generating IP output products