What options are available in Vivado to reduce the simulation runtime with the minimum impact on the functionality of my 7 Series design?
The UNIFAST library is an optional library that can be used during RTL behavioral simulation to speed up simulation runtime of 7 Series designs.
Xilinx recommends using the UNIFAST library for initial verification of the design and when running a complete verification use the UNISIM library.
The simulation runtime speed-up is achieved by supporting a subset of the 7 Series primitive features in the simulation mode.
The 7 Series primitives listed below have an equivalent UNIFAST model:
The UNIFAST model is provided in both VHDL & Verilog versions and is located in the following directories:
Recommended method for simulation with all UNIFAST models:
To enable UNIFAST support in a Vivado project environment for the Vivado simulator or ModelSim, check the Enable fast simulation models box, as shown below: