1. Locate the file ddr3_model.v in the Sources window and go to Source File properties.
Click the Button next to Type.
2. Change the File Type to System Verilog from Verilog as shown in the Figure below:
(Note: You may see a Critical Warning on Line 405 of ddr3_model.v file after this change which can be ignored)
3. If using TCL, use the command:
set_property file_type SystemVerilog [get_files mig_7series_0_example.srcs/sim_1/imports/sim/ddr3_model.v]
4. Run the Simulation in Vivado Simulator.