UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59657

Vivado Implementation - [Drc 23-20] Rule violation (PDRC-154) Physical design rule - Invalid the driving cell XX_1 is not adjacent below it configuration: is not adjacent below it configuration:

Description

During the write_bitstream stage, I receive the following DRC error message:

[Drc 23-20] Rule violation (PDRC-154) Physical design rule - Invalid the driving cell XX_1 is not adjacent below it configuration: is not adjacent below it configuration:
 Cell XX_2 has OPMODE[6:0] set to x01xxxx (use PCIN bus), but cell placement to supply the connections to a PCOUT bus. 
 The OPMODE or DSP48E1 should be changed to fix this invalid condition. If a '0' input is needed, the ZMUX select should be changed so the OPMODE would be 000xxxx.

Why does this DRC violation occurs?

Solution

There are cascaded DSP primitives in the design. 

These DSPs are connected from the PCOUT pin of the upstream DSP to the PCIN pin of the downstream DSP. 

This is the dedicated route, and the DSP should be placed in the adjacent location.

This is a valid DRC error message.

If you receive the error message, check why the cascaded DSPs are not placed in the adjacent location. 

AR# 59657
Date Created 03/05/2014
Last Updated 03/23/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite