AR# 59678


Vivado HLS 2013.4, 2014.1: FFT, FIR designs and examples: incorrect values are reported and are not updated


In Vivado HLS 2013.4 or 2014.1, for designs using the Xilinx FFT or FIR IP and the provided example designs, the reported values for latency, interval and resources occasionally do no match.

Also if implementation parameters are changed, the report does not update to reflect the changes.

Why does this occur?


In the 2013.4 and 2014.1 versions, the Vivado HLS tool always reports the estimations of the FFT/FIR with default parameters, it does not update the estimations when parameters are changed.

The Xilinx IP functions for the FFT and FIR are instantiated from the C source code.

However there is no C code to run the C-Synthesis to guide estimations.

The tool reports default values that are not updated by VHLS.

In order to get updated values, the C/RTL Co-Simulation and Vivado flow need to be run. 

Obtaining the waveform will allow it to measure the latency and II (VHLS reports it).

After Vivado synthesis and implementation, the resources figures will be available.

The TCL commands to be used in a script are:



export_design -evaluate verilog (or vhdl)

The results will be available in the report files.

 The estimations will be improved in future releases of the Vivado HLS tool.

The Vivado HLS User Guide UG902 lists the documentation for the FFT and FIR.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 59678
Date 07/01/2014
Status Active
Type Known Issues
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