FPGA Express 3.1: unexpected errors, access violation (0xc0000005), Dr. Watson
KEYWORDS: Dr. Watson, FPGA Express, access violation, 0xc0000005
GENERAL DESCRIPTION: When trying to synthesize HDL source code using FPGA Express or Foundation Express, users may occasionally run into Synopsys unexpected errors. Some examples:
An application error has occurred and an application error log is being generated. fexp.exe Exception: access violation (0xc0000005), Address 0x10082667
PCM - cannot get chips infor from Synopsys -- unknown error.
Synopsys Internal Error Abort at 1546
Dr. Watson, Access violation (Windows NT only)
These errors typically occur due to unexpected syntax in the HDL code. Here are some suggestions that may help you work around these errors:
Before synthesizing the design:
Set Effort to "Low" Set Optimization strategy to "Area" Check the "Preserve Hierarchy" box
In the Constraints Editor, under the Modules tab:
Set Operator Sharing to "Off" Set Duplicate Register Merge to "Disable" The global settings above can also be done here on a modular basis.
Even if the problem can be worked around, there is an issue that needs to be resolved. Work with the Xilinx hotline to determine the root cause of the unexpected error. Finding a solution often requires submission of your design (or at least a testcase) so we can reproduce the problem.