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AR# 59770

Vivado DSP Tools (System Generator for DSP) (2014.1) - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for System Generator for DSP 2014.1

Solution

Installation instructions and a list of the Release Notes and Known Issues in System Generator for DSP 2014.1 tools are included in this answer record. 

A successful installation of Vivado Design Suite 2014.1 changes your design tools version number to 2014.1.

Release Notes and New Features in System Generator for DSP 2014.1

For a list and description of the new features and Release Notes in the 2014.1 tools, see the Vivado Design Suite User Guide - Release Notes, Installation and Licensing (UG973): http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug973-vivado-release-notes-install-license.pdf

Please be sure to read the documentation because it answers questions that you might have about changes to the functionality or the look-and-feel from previous versions of System Generator for DSP. 

The Vivado Design Suite User Guide - Model-Based DSP Design using System Generator is accessible in PDF format at: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug897-vivado-sysgen-user.pdf.

For System Generator for DSP Release Notes for other versions, see (Xilinx Answer 29595).

Note: For Vivado Design Suite Model Based DSP Design using System Generator from 2013.1 and supported OS and MATLAB versions, please see (Xilinx Answer 55830).

General

(Xilinx Answer 53806) - Vivado System Generator - How can I use the legacy designs in Vivado Sysgen?
(Xilinx Answer 52571) - Vivado System Generator - Does Vivado SysGen use CoreGen or IP Catalog in the backend?
(Xilinx Answer 47623) - Vivado DSP Tools - System Generator for DSP 2012.1 - Why do I get critical warnings on pin locations and constraints not applied for a model in a design with multiple unique SysGen submodules?
(Xilinx Answer 52330) - Vivado System Generator - How do I configure MATLAB with Vivado System Generator?
(Xilinx Answer 58441) - System generator for DSP 2013.3 -xlTimingAnalysis error
(Xilinx Answer 58175) - 2013.3 SysGen - IP Packager flow does not provide zipped packaged IP
(Xilinx Answer 60311) - Vivado System Generator - When does Vivado System Generator check out the license?

Resolved Issues

(Xilinx Answer 55825) - System Generator - FIFO, TO_/FROM_FIFO blocks do not simulate the latency correctly when "Use Embedded Register" is selected
(Xilinx Answer 58174) - 2013.3 SysGen - "ERROR: [VRFC 10-149] 'axis_output_buffer' is not compiled in library v_ccm_v6_0"
(Xilinx Answer 57644) - 2013.2 Vivado SysGen - Bitbasher expected an identifier at the start of an assignment at column 1 in line 1
(Xilinx Answer 57489) - 2013.2 SysGen - Upgrading model with DDS v5.0 to DDS v6.0 causes compilation error when simulating

Known Issues

(Xilinx Answer 60617) - 2014.1 Vivado System Generator - Closing a Xilinx Blockset block GUI using the "X" in the top right corner of the GUI can cause the block GUI to hang
(Xilinx Answer 59236)
- 2014.1 System Generator - Sysgen/Matlab library compatibility issues may occur with Sysgen 2014.1 on Linux OS
(Xilinx Answer 60187)
- 2014.1 System Generator - Waveform Viewer displays the incorrect clock period in multi-clock domain designs
(Xilinx Answer 58837)
- 2013.3 Vivado SysGen - Modelsim block produces errors in modelsim console: can't read "vsimPriv(windowmgr)": no such element in array /  # ** Error: Tree does not exist
(Xilinx Answer 58569)
- Vivado 2013.3 SysGen - Unable to make recursive copy for the .mdl file
(Xilinx Answer 58836)
- 2013.3 Vivado Sysgen - Blackbox block failing behavioral simulation with Data Mismatches for both VHDL and Verilog
(Xilinx Answer 56042)
- 2013.1 Vivado System Generator - Migrating from Vivado 2012.4 to 2013.1 will lead to different pinout on the HDL generated, no CE pin created in 2013.1
(Xilinx Answer 53961)
- Vivado SysGen - Several synthesis errors occur when using the IP Packager flow in Vivado if the path length exceeds 256 characters
(Xilinx Answer 57604)
- Why is the fractional width on the "reload_tdata_data" port no longer dynamic in the FIR Compiler?

AR# 59770
Date Created 03/13/2014
Last Updated 05/28/2014
Status Active
Type General Article
Tools
  • System Generator for DSP