When running write_bitstream on a design that has placed successfully, the following error is displayed:
This error is displayed if the user has instantiated more than one IDELAY_CTRL and has not applied LOC constraints to them.
If more than one is being used then Vivado cannot replicate the IDELAY_CTRLs and place them as required.
The user is required to ensure there are enough IDELAY_CTRL instances for all of the banks that use the IODELAYs and that the following LOC constraint is applied to them.
set_property LOC IDELAYCTRL_X?Y? [get_cells abc/xyz/idelayctrl.delayctrl]
X?Y? in the above correspond to the clock region the I/O pins are located in.
For automatic replication by creating generic IODELAY groups, see (Xilinx Answer 68753)