Description

A critically important aspect of debugging video designs is to ensure that the video stream is of the proper frame size and that it adheres to the given interface specification (which, for most Xilinx Video IP, is the Video over AXI4 Stream protocol).

The Video Debug Module provided with this article will help to ensure that a given video stream is well formed and does not contain any frame size errors.

Features of the Video Debug Module include:

• Frame, Line, and Pixel counters
• Frame size error checking
• Storage of 1024 previous frame sizes and error conditions (accessible via Tcl or C API)
• Programmable flag for triggering tools such as Vivado Logic Analyzer
• Optional AXI4-Lite or JTAG interface
• Easy-to-use software/Tcl API for interacting with the core

Solution

The Video Debug Module is provided as a packaged Vivado IP core which can be used like any other IP core in Vivado and/or IP Integrator.
Simply extract the attached zip file and add the parent directory to the IP Repository in any Vivado Project settings.
The Video Debug Module will then show up in your IP Catalog for use in your design.

The core contains an s_axis interface which is a packaged as a 'monitor' type interface so that it can be attached to an existing AXIS bus in an IP Integrator design.

Therefore, the core should be placed in the system as depicted here:

To use this core, download the xilinx.com_user_vid_dbg_module_3.1.zip file attached here, extract it, and point to it from the IP Repositories settings of any Vivado project.

It will then appear in the Vivado IP Catalog for use in HDL or IP Integrator designs. Tcl and C code are also included in the zip for interacting with the core.

For complete documentation on how to use the core and its Tcl/C APIs, refer to user_guide.pdf, which is also in the zip file.

Attachments

Associated Attachments

Linked Answer Records

Master Answer Records

Associated Answer Records