We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59799

Vivado Constraints - How to avoid overwriting clock constraints when using create_clock constraints in scoped constraint files?


When using "create_clock -name" constraints in scoped constraint files (SCOPED_TO_REF, SCOPED_TO_CELLS), the following warning can be observed when opening the synthesized design or implemented design, or during synthesis or implementation.

WARNING: [Constraints 18-619] A clock with name '<clock name>' already exists, overwriting the previous clock with the same name.

What is the recommended solution to avoid overwriting create_clock constraints?


This warning is displayed when there are multiple instances of the scoped cells/ref in the design so the same "create_clock -name" constraint is read multiple times.

Only the last one read remains and all of the others are lost, as indicated in the warning message.

The recommended solution is to remove the -name option from the create_clock command.

If the -name option is not used, the system creates a unique name based on the netname/location.

All references to these automatically named clocks can be done via " get_clocks -of ".

For example:

create_clock -name recclk -period 5 [get_pins gt_and_clocks_i/gtwizard_i/gt0_gtwizard_i/gtxe2_i/RXOUTCLK];
set_false_path -from $cpri_v6_1_aux_clk -to [all_registers -clock recclk]

Is equivalent to:

create_clock -period 5 [get_pins gt_and_clocks_i/gtwizard_i/gt0_gtwizard_i/gtxe2_i/RXOUTCLK];  #-name cpri_v6_1_recclk
set recclk [get_clocks -of [get_pins gt_and_clocks_i/gtwizard_i/gt0_gtwizard_i/gtxe2_i/RXOUTCLK]]
set_false_path -from $cpri_v6_1_aux_clk -to [all_registers -clock $recclk]

AR# 59799
Date 03/21/2016
Status Active
Type General Article
Page Bookmarked